Input/output data processing system

• US 4,315,310 A
• Filed: 09/28/1979
• Issued: 02/09/1982
• Est. Priority Date: 09/28/1979
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cox, George W., Kahn, Kevin C., Bayliss, John A., Forbes, Bert E.
• Primary Examiner(s): Nussbaum, Mark E.
• Assistant Examiner(s): Chan, Eddie P.
• Application Number:
  US06/079,991
• Time in Patent Office: 865 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/3
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: G06F 13/4208 being a system bus, e.g. VME bus, Futurebus, Multibus

Abstract

An input/output processor architecture for providing an interface between peripheral subsystems and a generalized data processor. The interface processor enables data to be transferred between two address spaces (the generalized data processor address space and an external processor I/O address space) by mapping a portion of the I/O address space into a portion of the GDP address space. This mapping facility provides the peripheral subsystem with a "window" into the associated GDP subsystem. It accepts addresses within a certain subrange, or subranges, and translates them into references into one or more GDP data segments.

A function-request facility provides a functional capability over certain objects within the GDP address space.

The two facilities provide software on an external processor with a window into the address space of the GDP that enables the software, via the function request means, to send messages to and receive messages from the GDP and to manipulate an environment provided for the external processor within its address space.

Claims

1. For use in a data processing system including a main processor of a type capable of executing an operation by means of an operator specified in an instruction, said operator being one of a set of main processor operators executable on said main processor, said system having instruction objects defining an operation, and data objects, said instruction objects and data objects being stored in a memory which can be shared by a number of processors, the instruction objects and data objects accessible to said main processor existing in an address space in said memory associated with said main processor,

an interface processor which enables an external processor to interface with said memory and said main processor, said external processor being capable of referencing an I/O address space associated with said external processor, said interface processor comprising:

means for receiving addresses and commands from said external processor, one of said commands being a particular command including bits in said particular command specifying a particular operator;

recognizing means connected to said receiving means for comparing said addresses from said external processor with address registers associated with each of a number of address blocks, each of said blocks falling within a predetermined address range within the I/O address space of said external processor,

said recognizing means including means for generating match signals, one match signal for each of said address blocks,

one of said address blocks including command register means for receiving said particular command from said external processor;

means connected to said recognizing means responsive to said match signals for mapping said addresses within said address range from the I/O address space of said external processor onto the address space of said main processor;

function request means connected to said command register means,

said function request means including means for executing a set of interface processor operators comprising access environment manipulation operators and communication operators in response to said match signal from said one of said address blocks containing said command register means,

said set of interface processor operators being a subset of said main processor operators,

one of said interface processor operators being said particular operator specified in said particular command,

said function request means including means responsive to said bits in said particular command for executing said particular operator,

whereby said external processor is able to make a request for the execution of said particular operator by said interface processor by sending an address corresponding to the address block in which said command register means is contained and writing a copy of said particular command into said command register means,

said function-request means thereby being capable of being invoked by commands contained in instructions within the I/O address space of said external processor;

first interface means for connecting said mapping means and said function-request means with said memory; and

,

second interface means for connecting said address and command receiving means with said external processor;

whereby said external processor is provided with a window, via said recognizing means, into the address space of said main processor,

said interface processor operators included in said function request means providing instruction set extensions to the operator set of said external processor to thereby allow a process executing on said external processor, via invoking execution of said communication operators on said function-request means, to send messages to said main processor, and to receive messages from said main processor, and via invoking execution of said access environment manipulation operators on said function-request means, to manipulate objects within said address space of said main processor.

2. The combination in accordance with claim 1 wherein,

said mapping means for mapping said addresses within said address range from the I/O address space of said external processor onto the address space of said main processor consists of N map entries capable of supporting the random mapping of N nonoverlapping address subranges from said external processor into corresponding data segments of the address space of said main processor and wherein,

said means connected to said receiving means for recognizing said addresses from said external processor includes means for recognizing that an address falls within one of said N address subranges within the I/O address space of said external processor.

3. The combination in accordance with claim 2 wherein one map entry of said N map entries and its associated external processor I/O address subrange always maps onto a current context-control segment within said address space of said main processor, whereby said external processor is able to have access to said context-control segment, thereby enabling said external processor to read current status information stored in said current context-control segment.

4. The combination in accordance with claim 3 wherein a copy of the information contained in each processor-resident map entry is represented within acid context-control segment by a data structure comprising a plurality of fields containing parameters for controlling and defining said mapped address range.

5. The combination in accordance with claim 4 wherein said data structure within said context-control segment includes a start address for specifying the starting address of the external processor address subrange mapped by said map entry and a displacement for specifying the extent of said subrange from said start address.

6. The combination in accordance with claim 3 wherein said function-request means is represented within said context-control segment by a data structure comprising a plurality of fields containing a copy of processor-resident information related to the current or most recent function requested, said information comprising function-state information, the op code of the operator requested, the operands operated upon in performing the requested function, and an area used to record the result of the requested function.

7. The combination in accordance with claim 1 wherein said access environment manipulation operators include a first map manipulation operator, the execution of which by said function-request means allows an operation on said external processor to alter the interaddress space mapping provided by one of said address subrange map entries.

8. The combination in accordance with claim 1 wherein said access environment manipulation operators include a second map manipulation operator, the execution of which by said function-request means allows an operation on said external processor to associate a given data segment with a given address subrange map entry.

9. The combination in accordance with claim 1 wherein said communication operators include a first communication operator, the execution of which allows an external processor to receive a signal after a delay of n times quanta.

10. The combination in accordance with claim 1 wherein at least one of said address blocks is dedicated to an I/O address subrange which maps, via said mapping means, onto a current context-control segment in said main processor address space, to thereby enable said external processor to have access to said context-control segment, thereby enabling said external processor to read current status information stored in said current context-control segment.

11. The combination in accordance with claim 1 wherein at least one of said address blocks has associated with it a register containing a segment descriptor which points to the base of a data segment within said main processor address space.