Servo loop processor

• US 4,316,193 A
• Filed: 10/01/1979
• Issued: 02/16/1982
• Est. Priority Date: 07/15/1974
• Status: Expired due to Term

• Current Assignee: The Boeing Co.
• Original Assignee: The Boeing Co.
• Inventors: Jones, Philip, Storey, Moorfield Jr.
• Primary Examiner(s): Blum, Theodore M.
• Application Number:
  US06/080,533
• Time in Patent Office: 869 Days
• Field of Search: 343/112 D, 343/7A
• US Class Current: 342/458
• CPC Class Codes: G01S 11/02 using radio waves G01S19/00 takes precedence
• CPC Class Codes: G01S 3/50 the waves arriving at the antennas being pulse modulated and the time difference of their arrival being measured

Abstract

A servo loop processor suitable for use in a passive radar range determining system is disclosed. Early and late overlapping video pulse trains derived from spaced receiving antennas are fed to separate first and second channels and are sampled and held from pulse period to pulse period to form signals representing the amplitude envelopes of the received pulse trains. The output of the first channel is variably delayed and the delayed signal is compared with the undelayed output of the second channel to create an error signal. The output of the second channel is also differentiated, and the result is sampled and held to create a reference signal that has the proper phase relationship with the error signal so that the error signal can be multiplied by the reference signal to create a correction signal. The resulting correction signal is integrated and fed back to control the time delay applied to the output of the first channel such that a closed servo loop is formed. At balance, the integrated correction signal is related to the distance between the radar antenna transmitting the pulse trains, and the receiving antennas. In an alternative embodiment, envelope signals representing the first and second channel pulse trains are converted from analog to digital form, and the digitized second channel output is subtracted from the same digitized signal delayed by a fixed interval to form a digital version of the above-mentioned reference signal. A digital version of the error signal, derived as above, is then multiplied by the digital reference signal to create a digital correction signal, which after integration, controls the time delay of the first channel output signal.

Claims

1. A servo loop processor suitable for use in determining the time shift between first and second like signals, said first signal occurring in time prior to said second signal, said servo loop processor comprising:

controllable delay means, connected to receive said first signal, for delaying said first signal, said controllable delay means having a delay control input;

comparison means for receiving said second signal and being coupled to the output of said delay means for receiving said delayed first signal, and for comparing said delayed first signal with said second signal and generating an error signal relating to the difference therebetween;

reference producing means for receiving said second signal, and for producing a reference signal in accordance therewith;

multiplier means, coupled to outputs of said comparison means and said reference producing means, for multiplying said error signal by said reference signal and for producing a correction signal in accordance therewith; and

,

delay control means, coupled to an output of said multiplier means and to the delay control input of said controllable delay means, for controlling said controllable delay means so that said first signal is delayed by an amount intended to bring it into time correspondence with said second signal at which point said error signal reduces to zero.

2. A servo loop processor as claimed in claim 1, including:

first envelope means, connected to receive said first signal, for producing a first envelope signal related to the envelope of said first signal, said first envelope signal being applied to said controllable delay means; and

,

a second envelope means, connected to receive said second signal, for producing a second envelope signal related to the envelope of said second signal, said second envelope signal being applied to said comparison means and to said reference producing means.

3. A servo loop processor as claimed in claim 2 wherein said comparison means comprises a differential amplifier and wherein said delay control means includes an integrator connected to the output of said multiplier means.

4. A servo loop processor as claimed in claim 3 wherein said delay control means also includes a voltage controlled monostable multivibrator, the unstable state of said voltage control monostable multivibrator being controlled by the output of said integrator, the output of said voltage controlled monostable multivibrator being connected to said delay means for controlling the delay created by said controllable delay means.

5. A servo loop processor as claimed in claim 4 wherein said reference producing means comprises a differentiator connected to the output of said second envelope means and a sample-and-hold circuit connected to the output of said differentiator, the output of said sample-and-hold circuit forming the reference signal that is applied to said multiplier means.

12. A servo loop processor as claimed in claim 1 wherein said reference producing means includes means for causing said reference signal to be substantially in quadrature with said second signal.

13. A servo loop processor as claimed in claim 12 wherein said reference producing means comprises signal subtraction means for producing said reference signal by subtracting a delayed version of said second signal from said second signal.

14. A servo loop processor as claimed in claim 13, further comprising:

first envelope detection means, connected to receive said first signal, said first envelope detection means including sample-and-hold circuit means for producing a first envelope signal that is a stepwise representation of the envelope of said first signal, said first envelope signal being applied to said delay means; and

,

a second envelope detection means, connected to receive said second signal, said second envelope detection means including sample-and-hold circuit means for producing a second envelope signal that is a stepwise representation of the envelope of said second signal, said second envelope signal being applied to said comparison means and to said reference producing means.

15. A servo loop processor as claimed in claim 14 wherein said reference producing means comprises:

differentiator means for differentiating said second envelope signal to produce a bipolar pulse train signal; and

,

an additional sample-and-hold circuit means for detecting the envelope of said biopolar pulse train signal produced by said differentiator means, said additional sample-and-hold circuit means producing said reference signal.

16. A servo loop processor as claimed in claim 13 wherein said subtraction means of said reference producing means comprises a fixed delay means for receiving said second signal and delaying it by a first predetermined interval, and a difference taking means for receiving said second signal and for receiving the delayed second signal at the output of said fixed delay means, said difference taking circuit means having an output producing said reference signal that is the difference between said second signal and said second signal delay by said fixed delay interval.

17. A servo loop processor as claimed in claim 16 wherein said fixed delay means has a second delay output that produces a version of said second signal delayed by a second predetermined interval that is less than said first predetermined interval, and further comprising an additional fixed delay means connected in series with said controllable delay means so that said first signal is delayed by a controllable amount in said controllable delay means and by said second predetermined interval in said additional fixed delay means, and said comparison means is connected to said second output of said fixed delay means for receiving said second signal delayed by said second predetermined interval, and said comparison means is connected to receive said first signal delayed by both said controllable delay means and the serially connected additional fixed delay means, whereby said delay control means is responsive to said error signal and said reference signal for operating said delay control input of said controllable delay means so as to delay said first signal as it appears at said comparison means by an amount tending to bring said first signal into time correspondence with the version of said second signal delayed by said second predetermined interval.

18. A servo loop processor as claimed in claim 2, further comprising:

first analog-to-digital conversion means connected to said first envelope means for digitally encoding said first envelope signal and applying the resulting digitally encoded first envelope signal to said controllable delay means; and

,

a second analog-to-digital conversion means connected to said second envelope means for digitally encoding said second envelope signal and for coupling the digitally encoded second envelope signal to said comparison means and said reference producing means.

6. A servo loop processor suitable for use in a passive radar range determining system adapted to receive video pulse trains, generated by a transmitting radar antenna, at two spaced receiving antennas, the envelopes of said video pulse trains overlapping to the point that they are almost, but not quite, coincident, said servo loop processor comprising:

a first envelope generating means connected to receive the earliest occurring video pulse train, for generating a first envelope signal related to the envelope of the waveform of said earliest video pulse train;

a second envelope generating means, connected to receive the latest occurring video pulse train, for generating a second envelope signal related to the envelope of the waveform of said latest video pulse train;

control means for controlling said first and second envelope generating means;

reference signal generating means connected to said second envelope generating means for generating a reference signal in accordance therewith, said reference signal having a quadrature relationship with said second envelope signal; and

,

servo loop means, connected to receive said reference signal, the output of said first envelope generating means and the output of said second envelope generating means, for controllably delaying the output of said first envelope generating means as a function of a multiplication of said reference signal by an error signal that represents the difference between said delayed output of said first envelope generating means and said output of said second envelope generating means, until said delayed output corresponds in time to the output of said second envelope generating means.

7. A servo loop processor suitable for use in a passive radar range determining system as claimed in claim 6 wherein said servo loop means includes a delay means connected to the output of said first envelope generating means for delaying the output thereof, and a differential amplifier connected to the output of said second envelope generating means and to the output of said delay means for comparing the output of said delay means with the output of said second envelope generating means and generating said error signal in accordance therewith.

8. A servo loop processor suitable for use in a passive radar range determining system as claimed in claim 7 wherein said servo loop also includes:

a multiplier, said multiplier connected to receive said error signal and said reference signal, multiply them together and generate a correction signal in accordance therewith;

an integrator connected to the output of said multiplier; and

,

a delay control connected to the output of said integrator, the output of said delay control being connected to said delay means to control the delay created by said delay means.

9. A servo loop processor suitable for use in a passive radar range determining system as claimed in claim 8 wherein said first and second envelope generating means comprise first and second sample-and-hold circuits, respectively, and wherein said control means comprises sample pulse multivibrators connected to apply sample commands to said first and second sample-and-hold circuits upon the occurrence of a main or a side lobe in one of said video pulse trains.

10. A servo loop processor suitable for use in a passive radar range determining system as claimed in claim 9 wherein said delay means comprises a third sample-and-hold circuit and wherein said delay control comprises a voltage controlled monostable multivibrator having its unstable state control input connected to the output of said integrator and its trigger input connected to an output of said sample pluse multivibrators, the output of said voltage controlled monostable multivibrator connected to the command input of said third sample-and-hold circuit.

11. A servo loop processor suitable for use in a passive radar range determining system as claimed in claim 10 wherein said reference signal generating means comprises a differentiator connected to the output of said second sample-and-hold circuit and a fourth sample-and-hold circuit connected to the output of said differentiator, the output of said fourth sample-and-hold circuit forming said reference signal and being connected to said multiplier, said fourth sample-and-hold circuit being connected to an output of said sample pulse multivibrator so as to be sample commanded slightly after the triggering of said first and second sample-and-hold circuits.

19. A servo loop processor suitable for use in a passive system for monitoring a radar signal source that transmits a train of video pulses, and in which the passive system is associated with antennas that receive the pulse train at a finite time differential characterized by the envelopes of the received video pulse trains overlapping to the point that they are almost, but not quite, coincident, said servo loop processor comprising:

first envelope detection means connected to receive the earliest occurring video pulse train, for generating a first envelope signal related to the envelope of said earliest occurring video pulse train;

second envelope detection means, connected to receive the latest occurring video pulse train, for generating a second envelope signal related to the envelope of said latest occurring video pulse train;

first fixed delay means for receiving said second envelope signal and having a first delay output producing a version of said second envelope signal delayed by a first predetermined interval, and having a second delay output for producing a version of said second envelope signal having a second predetermined delay interval, wherein said second predetermined delay interval is less than said first predetermined delay interval;

a controllable delay means, connected to receive said first envelope signal, for delaying said first envelope signal, said controllable delay means having a delay control input;

a second fixed delay means connected in series with said controllable delay means for delaying said first envelope signal by an additional amount equal to said second predetermined delay interval of said second output of said first fixed delay means;

comparison means for receiving said first envelope signal after it has been delayed by said controllable delay means and by said second fixed delay means, and for receiving said second envelope signal from said second output of said first fixed delay means and thus after said second envelope signal has been delayed by said second predetermined interval, said comparison means comparing the thusly delayed first and second envelope signals and generating an error signal relating to the difference therebetween;

reference signal subtraction means coupled to the first output of said fixed delay means and to said second envelope detection means for subtracting said first envelope signal delayed by said first predetermined interval from the undelayed first envelope signal so as to produce a reference signal having a predetermined phase relationship with said second envelope signal;

multiplier means coupled to receive said reference signal from said reference signal subtraction means and to receive said error signal from said comparison means, and for multiplying said error signal by said reference signal to produce a correction signal in accordance therewith; and

,

delay control means coupled to an output of said multiplier means and to said delay control input of said controllable delay means, for controlling said controllable delay means so that said first envelope signal as delayed and applied to said comparison means is controllably delayed by an amount tending to bring it into time correspondence with said second envelope signal delayed by said second predetermined interval and applied to said comparison means.

20. A servo loop processor as claimed in claim 19, further comprising:

first analog-to-digital conversion means connected between said first envelope detection means and the serially connected controllable time delay means and second fixed time delay means, for digitally encoding said first envelope signal prior to it being applied to said controllable time delay means and said second fixed time delay means; and

second analog-to-digital conversion means connected between said second envelope detection means and said first fixed interval delay means, for digitally encoding said second envelope signal prior to it being applied to said first fixed time delay means.

21. A servo loop processor as claimed in claim 20 wherein said reference signal subtraction means comprises a digital subtractor, and said reference signal produced thereby is digitally encoded;

and wherein said comparison means comprises a digital subtractor, and said error signal produced thereby is digitally encoded.

22. A servo loop processor as claimed in claim 21 wherein said multiplier means comprises means for digitally multiplying said digitally encoded error signal by said digitally encoded reference signal to produce a digitally encoded correction signal.