Low power consumption data processing system

• US 4,316,247 A
• Filed: 10/30/1979
• Issued: 02/16/1982
• Est. Priority Date: 10/30/1979
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Iwamoto, Eisaburo
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Chan, Eddie Pang
• Application Number:
  US06/089,708
• Time in Patent Office: 840 Days
• Field of Search: 365/222, 365/226, 365/227, 365/228, 364/200 MS File, 364/900 MS File, 364/707
• US Class Current: 713/321
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Abstract

A data processing system which contains a read-only memory circuit, an arithmetic circuit, and a control circuit on a single semiconductor chip including a clock generating circuit for supplying system clocks to all of the circuits on the chip and the clock generating circuit is structured such that on the input of an external halt signal, the clock circuits will cease supplying system clocks during a period that provides for information contained within the system on the semiconductor chip.

Claims

1. An electronic data processing system including a read-only memory, a random-access memory, an arithmetic circuit and a control circuit, all structured using complementary field-effect transistors and all receiving external power during normal operation further comprising:

a clock circuit for simultaneously and repetitively generating a plurality of clock phases during a cycle, means for coupling said clock phases to said read-only memory circuit, said random access memory circuit, said arithmetic circuit and said control circuit;

a halt input terminal circuit coupled to said clock circuit for stopping said clock circuit from generating said clock phases and responsive to a halt input and one of said clock phases representing the time which allows the maintenance of information contained in said system without continued operation of said clock circuit, whereby the only power requirement during the stopping of said clock circuit is to refresh said random-access memory thereby conserving power.

2. An electronic data processing system according to claim 1, wherein said read-only memory circuit, said arithmetic circuit and said control circuit are constructed as dynamic logic.

3. An electronic data processing system according to claim 1, wherein said random-access memory circuit is structured as static logic.

4. An electronic data processing device all structured using complementary field-effect transistors implemented on a single semiconductor substrate and all receiving external power during normal operation comprising:

a read-only memory for the storage of instructions;

a random-access memory for the storage of data;

a control circuit which provides control signals in response to said instructions;

an arithmetic circuit which performs operations on said data in response to said control signals;

a clock circuit for simultaneously and repetitively generating a plurality of clock phases during a cycle, means for coupling said clock phases to said read-only memory circuit, said random-access memory circuit, said arithmetic circuit and said control circuit;

a halt input terminal circuit coupled to said clock circuit for stopping said clock circuit from generating said clock phases and responsive to a halt input and one of said clock phases representing the time which allows the maintenance of information contained in said system without continued operation of said clock circuit, whereby the only power required during the stopping of said clock circuit is to refresh said random-access memory thereby conserving power.

5. An electronic data processor device according to claim 4, wherein said read-only memory circuit, said arithmetic circuit and said control circuit are constructed as dynamic logic.

6. An electronic data processor device according to claim 5, wherein said random-access memory circuit is structured as static logic.