High-voltage circuit for insulated gate field-effect transistor

• US 4,317,055 A
• Filed: 05/08/1979
• Issued: 02/23/1982
• Est. Priority Date: 05/24/1978
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Nagata, Minoru, Katto, Hisao, Ochi, Shikayuki, Yoshida, Isao
• Primary Examiner(s): Anagnos, Larry N.
• Application Number:
  US06/036,972
• Time in Patent Office: 1,022 Days
• Field of Search: 307/200 B, 307/251, 307/304, 307/296 R, 307/584, 330/277
• US Class Current: 327/541
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03F 1/22 by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 3/42 Amplifiers with two or more amplifying elements having their dc paths in series with the load, the control electrode of each element being excited by at least part of the input signal, e.g. so-called totem-pole amplifiers
• CPC Class Codes: H03F 3/423 with MOSFET's
• CPC Class Codes: H03K 17/567 Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT

Abstract

A high-voltage circuit for insulated gate field-effect transistors (MOSFETs) is provided wherein two MOSFETs are connected in series, the source and gate of the first MOSFET being respectively used as a source terminal and gate terminal of the high-voltage circuit, the drain of the second MOSFET being used as a drain terminal of the circuit. First and second resistors are connected in series between the source terminal and the drain terminal, and a biasing voltage supply is connected between the juncture of both the resistors and the gate of the second MOSFET. By virtue of these connections the "on" resistance of the high-voltage circuit is improved due to the effect of the biasing voltage effect in bringing the second MOSFET into an "on" condition.

Claims

1. A high-voltage MOSFET (insulated gate field-effect transistor) circuit wherein n MOSFETs are connected in series by electrically connecting a drain of the m-th (1≦

m≦

n-1) MOSFET and a source of the (m+1)-th MOSFET, a source and gate of the first MOSFET being respectively used as a source terminal and gate terminal of the MOSFET circuit, a drain of the n-th MOSFET being used as a drain terminal of the MOSFET circuit, and wherein divided voltages obtained by dividing a voltage applied across the source and drain terminals, by means of a first voltage divider circuit in which a plurality of resistors are connected in series are applied to gates of the second to n-th MOSFETs;

the high-voltage MOSFET circuit being characterized by comprising means for holding the second to n-th MOSFETs in an "on" state by applying bias voltages from a bias voltage supply to the respective gates of said second to n-th MOSFETs.

2. A high-voltage circuit for MOSFETs according to claim 1, wherein said means for applying bias voltages comprise bias voltage supply means electrically connected between said respective gates of said second to n-th MOSFETs and connection nodes of said resistors of said first voltage divider circuit.

3. A high-voltage circuit for MOSFETs according to claim 1, wherein said bias voltage supply means is connected to said gates through rectifiers.

4. A high-voltage circuit for MOSFETs according to claim 1, wherein said means for applying bias voltages is a circuit which divides a voltage fed from a bias voltage supply terminal, by means of a second voltage divider circuit with a plurality of resistors connected in series and which applies the divided voltages to said respective gates as said bias voltages.

5. A high-voltage circuit for MOSFETs according to claim 4, wherein one of connection nodes of said resistors of said second voltage divider circuit is connected to an end of said first voltage divider circuit.

6. A high-voltage circuit for MOSFETs according to claim 4, wherein connection nodes of said resistors of said second voltage divider circuit are connected to said respective gates of said second to n-th MOSFETs through rectifiers.

7. A high-voltage circuit for MOSFETs according to claim 1, wherein an impedance element having a threshold value is inserted between the adjacent resistors of said first voltage divider circuit, whereby said bias voltages are applied to said respective gates of said second to n-th MOSFETs.

8. A high-voltage circuit for MOSFETs according to claim 7, wherein said impedance element having a threshold value is a Zener diode.

9. A high-voltage circuit for MOSFETs according to claim 8, wherein said impedance element having a threshold value is a diode-coupled bipolar transistor.

10. A high-voltage MOSFET (insulated gate field-effect transistor) circuit wherein n MOSFETs are connected in series by electrically connecting a drain of the m-th (1≦

m≦

n-1) MOSFET and a source of the (m+1)-th MOSFET, a source and gate of the first MOSFET being respectively used as a source terminal and gate terminal of the MOSFET circuit, a drain of the n-th MOSFET being used as a drain terminal of the MOSFET circuit, and wherein divided voltages obtained by dividing a voltage applied across the source and drain terminals, by means of a first voltage divider circuit in which a plurality of resistors are connected in series are applied to gates of the second to n-th MOSFETs;

the high-voltage MOSFET circuit being characterized by comprising means for applying bias voltages from a bias voltage supply to the respective gates of said second to n-th MOSFETs, wherein said bias voltage supply means is connected to said gates through rectifiers.

11. A high-voltage MOSFET (insulated gate field-effect transistor) circuit wherein n MOSFETs are connected in series by electrically connecting a drain of the m-th (1≦

m≦

n-1) MOSFET and a source of the (m+1)-th MOSFET, a source and gate of the first MOSFET being respectively used as a source terminal and gate terminal of the MOSFET circuit, a drain of the n-th MOSFET being used as a drain terminal of the MOSFET circuit, and wherein divided voltages obtained by dividing a voltage applied across the source and drain terminals, by means of a first voltage divider circuit in which a plurality of resistors are connected in series are applied to gates of the second to n-th MOSFETs;

the high-voltage MOSFET circuit being characterized by comprising means for applying bias voltages from a bias voltage supply to the respective gates of said second to n-th MOSFETs, wherein said means for applying bias voltages is a circuit which divides a voltage fed from a bias voltage supply terminal, by means of a second voltage divider circuit with a plurality of resistors connected in series and which applies the divided voltages to said respective gates as said bias voltages.

12. A high-voltage MOSFET (insulated gate fieldeffect transistor) circuit wherein n MOSFETs are connected in series by electrically connecting a drain of the m-th (1≦

M≦

n-1) MOSFET and a source of the (m+1)-th MOSFET, a source and gate of the first MOSFET being respectively used as a source terminal and gate terminal of the MOSFET circuit, a drain of the n-th MOSFET being used as a drain terminal of the MOSFET circuit, and wherein divided voltages obtained by dividing a voltage applied across the source and drain terminals, by means of a first voltage divider circuit in which a plurality of resistors are connected in series are applied to gates of the second to n-th MOSFETs;

the high-voltage MOSFET circuit being characterized by comprising means for applying bias voltages from a bias voltage supply to the respective gates of said second to n-th MOSFETs, wherein an impedance element having a threshold value is inserted between the adjacent resistors of said first voltage divider circuit, whereby said bias voltages are applied to said respective gates of said second to n-th MOSFETS.