Inverter having improved efficiency and regulation

• US 4,317,165 A
• Filed: 06/17/1980
• Issued: 02/23/1982
• Est. Priority Date: 06/17/1980
• Status: Expired due to Term

• Current Assignee: Vanner, Inc. (Vanner Holdings, Inc.)
• Original Assignee: Vanner, Inc. (Vanner Holdings, Inc.)
• Inventors: Sullivan, James D.
• Primary Examiner(s): Shoop, William M.
• Application Number:
  US06/160,555
• Time in Patent Office: 616 Days
• Field of Search: 331/114, 363/97, 363/41, 363/133, 363/134
• US Class Current: 363/41
• CPC Class Codes: H02M 7/53846 Control circuits

Abstract

An inverter circuit is disclosed in which the efficiency of the inverter is improved by interposing a small transformer winding between the transistors in a Darlington pair which are used to switch the primary current of the inverter. The winding couples energy from the transformer into the Darlington pair at a polarity which opposes the characteristic junction potential of the output transistor. This substantially reduces the saturation voltage of this output transistor. The regulation of the output voltage is improved by detecting the RMS value of the output voltage and using the detected RMS value of the output voltage for controlling the width of pulses applied to the primary of the transformer of the inverter.

Claims

1. In an inverter circuit of the type including a transformer having a center tapped primary to which a dc source is connected, a pair of push-pull connected bipolar transistor switching means connected to the ends of said primary for alternately applying said dc source to opposite halves of said primary, said switching means each having a control input, and a control means connected to said control inputs to control the alternate switching of said switching means, the improvement comprising:

a pair of windings, magnetically coupled to said transformer, a different one of said pair of windings connected in series with the control input circuit of each of said switching means, wherein each of said switching means comprises a pair of Darlington-connected bipolar transistors having said winding as the circuit element connecting the base of the output one of a said Darlington pair to the output of the input one of said Darlington pair.

2. An inverter circuit in accordance with claim 1 wherein said Darlington pairs are connected in a common collector circuit configuration.

3. An inverter circuit in accordance with claim 2 wherein said windings are connected in a polarity for positive feedback said Darlington pairs and have magnetic coupling for applying an induced voltage which is at least equal to the sum of the characteristic base-emitter junction voltages of the transistors of each of said pairs.

4. An inverter in accordance with claim 3 wherein a diode is shunted across the output switching terminals of each of said Darlington pairs and having a conduction polarity opposite to that of its associated parallel transistor.

5. An inverter in accordance with claim 4 wherein a pair of series connected diodes having their like terminals connected at their intermediate node are connected across the control inputs of said switching means and a zener diode is connected between said node and ground for clamping the output of said switching means below its breakdown voltage.

6. An inverter in accordance with claim 4 wherein said control means includes a time delay interval after turning off one switching means and before turning on the other and wherein a series resistance and capacitance are shunted across the output secondary of said transformer having a time constant which is substantial with respect to said time interval.

7. In an inverter of the type including a transformer to which a DC voltage is periodically applied by switching means, pulse width modulating control means for maintaining a constant AC output voltage by controlling the on-time of said switching means in response to output voltage, said pulse width modulating control means being responsive to the difference between a reference signal and the level of a feedback signal at the output of a feedback circuit, the signal being derived from the AC output voltage, the improvement comprising an RMS voltage detector circuit means as said feedback circuit, said RMS voltage detector converting the AC output voltage to a voltage level which is proportional to the RMS value of the output voltage.

8. In an inverter of the type including a transformer having the inverter output at its secondary and having a primary to which a DC voltage is periodically applied through at least one bipolar transistor switching means said inverter also having a square wave generator and a pulse width modulating controlling means connected to said square wave generator for maintaining a constant AC output voltage by controlling the on-time of said switching means, the improvement comprising:

(a) an output voltage detector circuit means connected to said secondary and the controlling means for detecting a signal which is proportional to the RMS value of the output voltage at said secondary for modulating the width of the pulses periodically applied to said primary; and

(b) at least one offsetting voltage source having an output connected to the input circuit of said transistor switching means and its input coupled to a source for providing a voltage which opposes the base-emitter junction voltage of the transistor switching means to reduce the emitter to collector voltage across the transistor switching means.

9. An inverter in accordance with claim 8 wherein said voltage source comprises an additional winding on said transformer.

10. An inverter in accordance with claim 9 wherein said inverter is a push-pull type having two of said transistor switching means each comprising a Darlington pair in a common collector configuration and wherein there are two of said windings each being connected between the base of the output of different ones of said Darlington pair and the emitter of the input one of different areas of said Darlington pair.

11. An inverter circuit comprising:

(a) a transformer having a center tapped primary;

(b) a DC source connected to the center tap of said primary;

(c) a pair of switching transistors connected to the ends of said primary and said DC source for switching current to said primary;

(d) a pair of windings magnetically coupled to said transformer and each connected to the input circuit of a different one of said switching transistors and having coupling selected to generate a voltage for opposing the input junction voltage of said switching transistor;

(e) an RMS detector circuit means having its input connected to the circuit of said secondary and having an output proportional to the RMS value of the inverter output voltage;

(f) a pulse generator; and

(g) a pulse width modulator connected to said pulse generator and said RMS detector circuit means for modulating the width of said pulses around a selected operating width in response to the difference between a reference signal and the output of said RMS detector circuit means.