Clocked logic low power standby mode

• US 4,317,180 A
• Filed: 12/26/1979
• Issued: 02/23/1982
• Est. Priority Date: 12/26/1979
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Lies, Kenneth A.
• Primary Examiner(s): Smith, Jerry
• Application Number:
  US06/106,429
• Time in Patent Office: 790 Days
• Field of Search: 364/705, 364/707, 364/200, 364/900, 307/24, 307/27, 307/28, 307/73, 307/75
• US Class Current: 713/321
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G06F 15/0216 Constructional details or arrangements
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An electronic data processing system such as utilized in battery powered hand held calculators having a two mode clock control for control of power consumption. A power consumption controller enables generation of clock signals in an active cycling state for operating the data processing system in an active mode and enables generation of clock signals in a predefined steady state for operating the data processing system in a low power standby mode. In another embodiment of this invention, the power consumption controller generates a preset signal during the standby mode, this preset signal being applied to certain critical circuits of the data processing system to force each critical circuit output to a designer predefined output logic level during the standby mode. The designer predefined output logic level of each critical circuit is selected to prevent static power loads in the standby mode caused by node self discharge.

Claims

1. An electronic data processing system having an ON mode and an OFF mode comprising:

a state controller means including means for generating a clock output in an active cycling state when said electronic data processing system is in said ON mode, means for generating said clock output in an inactive predetermined steady state when said electronic data processing system is in said OFF mode, and means for generating a preset signal at a predetermined voltage when said electronic data processing system is in said OFF mode; and

a plurality of circuit means, each coupled to said state controller means and each having an output terminal, each of said circuit means responsive to said active cycling state of said clock output for performing data processing functions in an active power mode, responsive to said steady state of said clock output for operating in a low power standby mode, and responsive to said predetermined voltage of said preset signal for generating a predetermined voltage at said output terminal.

2. The integrated circuit as in claim 1, wherein said circuit means are comprised of clocked logic.

3. An electronic data processing system having an ON mode and an OFF mode comprising:

a state controller means including means for generating a clock output in an active cycling state when said electronic data processing system is in said ON mode, and means for generating said clock output in an inactive predetermined steady state when said electronic data processing system is in said OFF mode; and

a plurality of circuit means, each coupled to said state controller means and each having an output terminal, each of said circuit means responsive to said active cycling state of said clock output for performing data processing functions in an active power mode, and responsive to said steady state of said clock output for operating in a low power standby mode and for generating a predetermined voltage at said output terminal.

4. An electronic data processing system as claimed in claim 3, wherein:

said state controller means further comprises means for generating a preset signal at a predetermined voltage when said electronic data processing system is in said OFF mode; and

said electronic data processing system further comprises at least one additional circuit means, each coupled to said state controller and having an output terminal, each additional circuit means responsive to said active cycling state of said clock output for performing data processing functions in an active power mode, responsive to said steady state of said clock output for operating in a low power standby mode, and responsive to said predetermined voltage of said preset signal for generating a predetermined voltage at said output terminal.

5. An electronic circuit having an ON mode and a STANDBY mode comprising:

controller means for selectively providing group select outputs at an active level when the electronic circuit is in the ON mode, and at an inactive level when the electronic circuit is in the STANDBY mode; and

clock means, connected to the controller means, for selectively generating group clock outputs in an active cycling state in response to receiving the active level group select outputs or for selectively generating group clock outputs in an inactive predefined steady state in response to receiving the inactive level group select outputs;

preset means for providing a preset signal when the electronic circuit is in the STANDBY mode; and

circuit group means connected to the clock means, the controller means, and to the preset means, selectively operable in an active power mode in response to receiving group clock outputs in the cycling state, and selectively operable in a standby power mode in response to receiving group clock outputs in the predefined steady state, said circuit group means including means for outputting a predetermined voltage in the standby power mode in response to receiving the preset signal.

6. The integrated circuit as in claim 5, wherein the circuit group means is comprised of ratioless logic.

7. The integrated circuit as in claim 5, wherein the circuit group means is comprised of clocked CMOS logic.

8. An electronic circuit having an ON mode and a STANDBY mode comprising:

controller means for selectively providing group select outputs at an active level when the electronic circuit is in the ON mode and at an inactive level when the electronic circuit is in the STANDBY mode; and

clock means, connected to the controller means, for selectively generating group clock outputs in an active cycling state in response to receiving the active level group select outputs or for selectively generating group clock outputs in an inactive predefined steady state in response to receiving the inactive level group select outputs; and

circuit group means connected to the clock means and the controller means, responsive to the cycling state of the group clock outputs for operating in an active power mode, and responsive to the steady state of the group clock outputs for operating in a standby power mode and for generating a predetermined voltage output.

9. An electronic circuit as claimed in claim 8, further comprising:

a preset means for providing a preset signal when the electronic circuit is in the STANDBY mode; and

additional circuit group means connected to the clock means, the controller means and the preset means, responsive to the cycling state of the group clock outputs for operating in an active power mode, responsive to the steady state of the group clock outputs for operating in a standby power mode, and responsive to the preset signal for generating a predetermined voltage output.