Multiple channel digital memory system

• US 4,318,183 A
• Filed: 12/22/1978
• Issued: 03/02/1982
• Est. Priority Date: 12/22/1978
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Pease, William M., Byington, Roy E.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US05/972,594
• Time in Patent Office: 1,166 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/602, 325/6, 179/15 A, 343/6.8 R, 343/6.8 L, 343/6.8 C, 365/45, 365/192, 365/197, 365/238, 365/244
• US Class Current: 710/72
• CPC Class Codes: G01R 13/345 for displaying sampled signals by using digital processors by intermediate A.D. and D.A. convertors (control circuits for CRT indicators)
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence

Abstract

A system for digitally storing samples of an analog signal taken at a sampling rate, f, and for reconstructing said analog signal from such stored samples. The analog signal is separated into a plurality of, n, channels, each one of such channels having a digital storage section. Each one of the storage sections is adapted to store a sample of the analog signal in response to a sampling pulse. A pulse generator circuit is provided and supplies one of a plurality of trains of periodic sampling pulses to a corresponding one of the plurality of storage sections. The sampling pulses in each of the trains of sampling pulses have a pulse repetition frequency, f/n. Further, the sampling pulses in successive trains thereof are delayed in time 1/nth the period of the sampling pulses. Apparatus is provided for retrieving the samples stored in the plurality of storage sections in the same sequence as such samples were stored. The sequentially retrieved samples are obtained at the rate, f, and are combined into a composite signal, such composite signal being a reconstruction of the analog signal. By using plural channels, each one of the storage sections samples the analog signal at a rate less than that required for a single channel system.

Claims

1. A system for digitally storing samples of the amplitude of an analog signal, such samples being taken at a constant sampling frequency, f, comprising:

(a) a plurality of, n, digital storage means, each one being fed, in parallel, by the analog signal and each one being adapted to store a train of samples of the amplitude of the analog signal fed thereto in response to a train of sampling pulses fed to such one of the plurality of digital storage means;

(b) means for producing a plurality of trains of the sampling pulses, each one of such trains of the sampling pulses having a pulse repetition frequency f/n, with the sampling pulses in the trains thereof being displaced in time, one from another, an amount 1/(nf); and

,

(c) means for feeding each one of the plurality of the produced trains of the sampling pulses to a corresponding one of the plurality of digital storage means.

2. The system recited in claim 1 wherein each one of the plurality of storage means comprises:

(a) a random access memory for storing data fed to input terminals thereof in response to a write control signal at an address fed to an address terminal of such random access memory and for reading data stored therein in response to a read control signal, such data being read from a location fed to the address terminals; and

(b) buffer storage means, fed by the analog signal, and responsive to the one of the plurality of trains of sampling pulses fed to such one of the plurality of digital storage means, for storing a series of successive samples of the analog signal and for enabling a predetermined plurality of such stored series of samples to be fed to the input terminal of the random access memory to be stored, in parallel, as data into such memory in response to the write control signal, for enabling a predetermined plurality of stored data to be read in parallel from the random access memory in response to the read control signal, and for coupling such read data as a series of samples to an output.

3. The system recited in claim 2 wherein such system includes a control section comprising:

(a) a read address means for producing the read addresses;

(b) a write address means for producing the write addresses; and

,

(c) a multiplexer having an output coupled to the address terminal of the random access memory, such multiplexer being fed by the read address means, the write address means, and a MUX control signal for coupling either the write address means or the read address means to the output of the multiplexer selectively in accordance with the MUX control signal.

4. The system recited in claim 3 wherein means are provided for producing the MUX control signal, such signal coupling the read address means to the output of the multiplexer during one portion of a clock cycle and for coupling the write address means to the output of the multiplexer during another portion of such clock cycle.

5. A system for digitally storing samples of the amplitude of an analog signal, such samples being taken at a constant sampling frequency, f, comprising:

(a) means for coupling the analog signal, in parallel, to a plurality of, n, signal channels;

(b) a plurality of, n, digital storage means, each one thereof being disposed in a corresponding one of the plurality of signal channels and each one thereof being fed by the analog signal, each one of the digital storage means being adapted to store a sample of the amplitude of the analog signal fed thereto in response to a sampling pulse fed to such one of the digital storage means;

(c) means for producing a plurality of, n, trains of the sampling pulses, each one of the plurality of trains of the sampling pulses having a pulse repetition frequency f/n, the sampling pulses in the trains thereof being displaced in time one from another an amount 1/(nf); and

(d) means for feeding each one of the plurality of produced trains of the sampling pulses to a corresponding one of the plurality of digital storage means.

6. The system recited in claim 5 wherein each one of the plurality of storage means comprises:

(a) a random access memory for storing data fed to input terminals thereof in response to a write control signal at an address fed to an address terminal of such random access memory and for reading data stored therein in response to a read control signal, such data being read from a location fed to the address terminals; and

(b) buffer storage means, fed by the analog signal, for storing a series of successive samples of the analog signal and for enabling a predetermined plurality of such stored series of samples to be fed to the input terminal of the random access memory to be stored, in parallel, as data into such memory in response to the write control signal, for enabling a predetermined plurality of stored data to be read in parallel from the random access memory in response to the read control signal, and for enabling such read data to be coupled as a series of samples to an output.

7. The system recited in claim 6 wherein such system includes a control section comprising:

(a) a read address means for producing the read addresses;

(b) a write address means for producing the write addresses; and

,

(c) a multiplexer having an output coupled to the address terminal of the random access memory, such multiplexer being fed by the read address means, the write address means, and a MUX control signal for coupling either the write address means or the read address means to the output of the multiplexer selectively in accordance with the MUX control signal.

8. The system recited in claim 7 wherein means are provided for producing the MUX control signal, such signal coupling the read address means to the output of the multiplexer during one portion of a clock cycle and for coupling the write address means to the output of the multiplexer during another portion of such clock cycle.

9. A system for digitally storing samples of the amplitude of an analog signal at a constant sampling frequency, f, and for reconstructing such analog signal from such stored samples, comprising:

(a) means for producing a plurality of, n, trains of sampling pulses, the sampling pulses in each of the trains thereof having a sampling frequency f/n;

(b) a plurality of digital storage means, each one thereof having an input fed in parallel by the analog signal and each one thereof being fed by a corresponding one of the plurality of trains of the sampling pulses, each one of such digital storage means storing a train of samples of the amplitude of the analog signal fed to the input thereof in response to a corresponding one of the plurality of trains of sampling pulses fed thereto; and

(c) means, fed by the plurality of digital storage means, for retrieving the samples stored in the plurality of digital storage means in the same sequence as such samples were stored in such plurality of digital storage means, including means for combining such sequentially retrieved samples into a composite signal, such composite signal being a reconstruction of the analog signal.

10. The system recited in claim 9 wherein each one of the plurality of storage means comprises:

(a) buffer storage means connected to the input of the digital storage means and fed by the analog signal for storing a series of successive samples of the analog signal and for coupling a predetermined plurality of such stored samples, in parallel, to a plurality of output terminals; and

,

(b) a random access memory means having a data input, a data output, a read/write control and an address input, such data input being coupled to the plurality of output terminals of the buffer storage means, for storing the samples coupled in parallel to the plurality of output terminals in response to a write control signal fed to the read/write control input, such samples being stored in such random access memory means at an address fed to the address input of such random access memory means and for reading samples stored therein in response to a read control signal fed to the read/write control input, such read samples being read from a location in such random access memory means fed to the address input, such read samples being coupled to the data output of such random access memory means, such data output being coupled to an input of the retrieving means.