Semiconductor device for the reproduction of acoustic signals

• US 4,318,188 A
• Filed: 05/21/1979
• Issued: 03/02/1982
• Est. Priority Date: 06/19/1978
• Status: Expired due to Term

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Hoffmann, Kurt
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/040,527
• Time in Patent Office: 1,016 Days
• Field of Search: 360/32, 365/45, 179/1 SM, 179/1 SA, 340/347 AD, 340/347 DA
• US Class Current: 360/32
• CPC Class Codes: G11C 19/186 using only one transistor per capacitor, e.g. bucket brigade shift register
• CPC Class Codes: G11C 19/287 Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 27/04 Shift registers
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

A microphone, for receiving an acoustic signal, is connected to a transducer which changes the analog signal delivered by the microphone into a sufficiently dense series of storable pulses in such a manner that the series contains the information necessary for the reproduction of the analog signal. The pulses delivered by the transducer can be pulse amplitude modulated (PAM) signals. The transducer must be connected to an analog memory. In the case where the signals are digital, such as pulse code modulated (PCM) signals, a digital memory is used. For reproduction, the pulses recalled from memory, in the first case, are fed via a low pass filter to an amplifier and a loud speaker. In the second case, the pulses are first converted into an analog form in a digital/analog converter. Stacked-gate injection metal-oxide-semiconductor (SIMOS) memories may be considered as the analog memories and, as digital memories, electrically alterable read-only memories (EAROM) may be utilized.

Claims

1. Apparatus for reproducing acoustic signals, comprising:

a microphone for transducing an acoustic signal into an analog electrical signal;

analog/digital converter means connected to said microphone and operable to convert the analog signals into a digital signal of discrete electrical pulses representing the information content of the acoustic signal;

semiconductor read/write memory means connectible to said analog/digital converter means for storing the information manifest in the digital signal;

digital/analog converter means connected to said read/write memory means and operable to convert the stored digital signal into an analog electrical signal which represents the original acoustic signal;

an input amplifier interposed between said microphone and said analog/digital converter;

a low pass filter connected to the output of said digital/analog converter means; and

an output amplifier connected to the output of said low pass filter,

wherein said memory means comprises an address counter including a timing pulse input, a plurality of parallel-connected non-volatile read/write memories each including a timing pulse input, each connected to said address counter, and each including a selection signal input, and means, including a timing pulse input, connected to said selection signal input and operable to generate selection signals for controlling the operation of said memories,

said analog/digital converter means including a timing pulse input,

said digital/analog converter means including a timing pulse input, and

each of said timing pulse inputs of said address counter, said read/write memories, said analog/digital converter means, and said digital/analog converter means, connected to receive the same timing pulses.

2. The apparatus of claim 1, wherein said analog/digital converter means comprises:

a digital/analog converter connected to said read/write memory means; and

a low pass filter connected to the output of said digital/analog memory.

3. The apparatus of claim 2, wherein:

said memory means comprises an address counter including a timing pulse input;

said analog/digital converter means includes a timing pulse input;

said digital/analog converter means includes a timing pulse input; and

said timing pulse inputs are connected to receive the same timing pulses.

4. The apparatus of claim 1, wherein said memory means comprises an electrically alterable read only memory.

5. The apparatus of claim 4, wherein said electrically alterable read only memory comprises stacked-gate injection metal-oxide-semiconductor memory cells.

6. Apparatus for producing an acoustic signal, comprising:

first transducer means for receiving and converting an acoustic signal into a corresponding analog electrical signal,

second transducer means for receiving and converting an analog electrical signal into a corresponding acoustic signal,

analog memory means connected between said first and second transducer means and operable to store said corresponding analog electrical signal and deliver said storage signal to said second transducer means for acoustic reproduction,

said analog memory means comprising a memory constructed of stacked-gate injection metal-oxide semi-conductor memory cells, and

said memory means comprising

a matrix including said memory cells, a plurality of word lines and a plurality of first and second bit lines,

each of said memory cells comprising a gate connected to a respective word line, a floating gate, a drain connected to a respective first bit line and a source connected to a respective second bit line,

a plurality of load transistors each including a source-drain path connected in series with a respective second bit line and a first potential and a gate connected to said first potential,

a write line for receiving a write signal,

a plurality of write transistors each including a source-drain path connected in series with the source-drain path of a respective load transistor and a gate connected to said write line,

an information output line,

a write mode transistor, a read mode transistor and an erase mode transistor, each of said mode transistors including a gate for receiving a respective write, read and erase signal and a source-drain path connected between said information output line and respective second, third and fourth potential,

a plurality of bit lines selection transistors each including a gate for receiving a bit selection signal and a source-drain path connected between a respective second bit line and said information output line,

programming means for deriving a programming signal from said analog signal,

an address generator operable to produce word line and bit line addresses,

a bit line decoder connected between said address generator and said gates of said bit line selection transistors, and

a word line decoder connected between said word lines and said address generator, said word line decoder including means connected to said programming means and operable to apply the programming signal to said gates of said memory cells which are connected to a selected word line.

7. The apparatus of claim 6, wherein said programming means comprises:

a sample and hold circuit connected between said first transducer means and said word line decoder.

8. The apparatus of claim 7, wherein said first transducer means comprises:

a microphone; and

an amplifier connected between said microphone and said sample and hold circuit.

9. The apparatus of claim 8, wherein said sample and hold circuit and said address generator each include a timing pulse input for synchronous operation.

10. The apparatus of claim 9, wherein said sample and hold circuit comprises:

a field effect transistor including a gate connected to said timing pulse input, and a source-drain path connected between said first transducer means and said word line decoder; and

a capacitor connected between said source-drain path and a reference potential.