Demodulator for amplitude modulated signal having high input impedance

• US 4,319,195 A
• Filed: 10/11/1979
• Issued: 03/09/1982
• Est. Priority Date: 10/11/1978
• Status: Expired due to Term

• Current Assignee: Nippon Electric Company Limited (NEC Corporation)
• Original Assignee: Nippon Electric Company Limited (NEC Corporation)
• Inventors: Matsumura, Eiichi
• Primary Examiner(s): Grimm, Siegfried H.
• Assistant Examiner(s): Westin, Edward P.
• Application Number:
  US06/083,709
• Time in Patent Office: 880 Days
• Field of Search: 455/337, 329/101, 329/164, 329/166, 329/168, 329/169, 329/204
• US Class Current: 329/364
• CPC Class Codes: H03D 1/18 of semiconductor devices

Abstract

A demodulator for demodulating an amplitude modulated signal of a carrier signal. The demodulator provides a high output and is suitable for use in integrated circuitry. An input signal is connected to the base of one transistor of a pair of transistors forming an input differential amplifier. The input differential amplifier is stably biased by means of a constant current generator, diodes, input resistors and collector resistors. The two opposite phase output voltages from the differential amplifier are applied to the bases of a pair of transistors which have their collectors and emitters tied together. The output from the latter transistor pair is taken from the common emitter connection and it is applied directly to the base of an emitter follower transistor, the output from the latter constituting an output from the demodulator circuitry. The particular circuit arrangement provides significant elimination of the carrier frequency and provides filtering by parasitic capacitances of the transistors.

Claims

1. A demodulator comprising:

an input terminal adapted to receive an amplitude modulated signal of a carrier signal;

means for deriving two intermediate output signals in response to said amplitude modulated signal, said two intermediate output signals having different phases from each other;

a first and a second transistor having their respective emitters connected in common, a base of said first transistor receiving one of said intermediate output signals, and a base of said second transistor receiving the other of said intermediate output signals;

an emitter follower transistor having a base exclusively connected to the emitters of said first and said second transistors the total capacitance of the parasitic capacitors associated with the emitters of said first and second transistors and the base of said emitter follower transistor being of a value sufficient for smoothing said carrier signal; and

an output terminal coupled to an emitter of said emitter follower transistor.

2. A demodulator claimed in claim 1, wherein said means for deriving two intermediate output signals includes a differential amplifier.

3. A demodulator claimed in claim 1 or 2, further comprising means for biasing said first and said second transistors into Class B or C operation.

4. A demodulator claimed in claim 1 or 2, wherein the collector of said first transistor is short-circuited to base thereof, and the collector of said second transistor is short-circuited to base thereof.

5. A demodulator claimed in claim 1 or 2, wherein collectors of said first and second transistors are connected in common.

6. A demodulator claimed in claim 3, wherein collectors of said first and second transistors are connected in common.

7. A demodulator claimed in claim 3, wherein the collector of the said first transistor is short-circuited to base thereof, and the collector of said second transistor is short-circuited to base thereof.

8. A demodulator claimed in claim 1, wherein the input impedance of said emitter follower transistor is primarily determined by an impedance component at said output end of said emitter follower transistor.

9. A demodulator comprising:

an input terminal receiving an amplitude modulated signal of a carrier signal;

a differential amplifier having an input end coupled to said input terminal; and

a first and a second output end deriving, respectively, a first and a second intermediate signal, phases of said first and said second intermediate signal being in opposite relation;

a first rectifying device having an input end receiving said first intermediate signal and an output end;

a second rectifying device having an input end receiving said second intermediate signal and an output end;

an emitter follower transistor having a base exclusively and directly connected to said output ends of said first and second rectifying devices, said carrier signal being smoothed by the parasitic capacitors of said first and second rectifying devices and said emitter follower transistor; and

an output terminal coupled to an emitter of said emitter follower transistor.

10. A demodulator claimed in claim 9, wherein said first and said second rectifying devices are transistors, said input ends of said first and said second rectifying devices are bases of said transistors, and said output ends of said first and said second rectifying devices are emitters of said transistors.