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System for detecting fades in television signals to delete commercials from recorded television broadcasts

  • US 4,319,286 A
  • Filed: 01/07/1980
  • Issued: 03/09/1982
  • Est. Priority Date: 01/07/1980
  • Status: Expired due to Term
First Claim
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1. A system for interrupting the recording process of a video tape recorder in the recordation of a television signal derived from a television receiver, said television signal including composite video signal components and audio signal components, said system including:

  • a first circuit means adapted to be connected to the video tape recorder and responsive to the video signal components of the television signal for producing an output signal having a particular reference level when the video signal components fade to a predetermined low amplitude for a particular time interval;

    detector means connected to said first circuit means and responsive to the output signal therefrom for developing an output pulse when the output signal from said first circuit means drops to said predetermined reference signal for said particular time intervals;

    trigger circuit means connected to said detector circuit means and responsive to the output pulse therefrom for producing a control signal of a predetermined duration;

    circuit means connected to said trigger circuit means and responsive to the control signal therefrom to interrupt the recording process of the video tape recorder for a time interval corresponding to the duration of said control signal;

    a further trigger circuit connected to the detector circuit means and responsive to the output pulse therefrom to be triggered from a reset state to a set state;

    circuitry connecting said further trigger circuit to said first-named trigger circuit to prevent said first-named trigger circuit from resetting so long as said second trigger circuit is in its reset state; and

    a third trigger circuit connected to said first-named trigger circuit to be triggered from its reset state to its set state when the first-named trigger circuit is triggered to its set state, said third trigger circuit remaining in its set state for a predetermined time interval, and circuitry connecting said third trigger circuit to said second trigger circuit to prevent said second trigger circuit from being set so long as said third trigger circuit is in its set state.

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