Method for fabricating IGFET integrated circuits

• US 4,319,396 A
• Filed: 12/28/1979
• Issued: 03/16/1982
• Est. Priority Date: 12/28/1979
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Inventors: Law, Hung-Fai S., Lopez, Alexander D.
• Primary Examiner(s): Walton, Donald L.
• Application Number:
  US06/108,289
• Time in Patent Office: 809 Days
• Field of Search: 29/571, 29/577 R, 29/576 R, 29/577 C, 365/72, 357/45
• US Class Current: 438/128
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

A rapid and systematic method for performing chip layout of a random-logic IGFET circuit includes steps for arranging the device features and interconnection features corresponding to the circuit in respective positions in an array of intersecting rows and columns. The method provides layouts of device and interconnection features having a high packing density and a high degree of order and regularity to facilitate checking for layout errors.

Claims

1. A method for fabricating a random-logic IGFET integrated circuit having a multiplicity of transistors in a prescribed arrangement, the method comprising the steps of:

(1) forming on a single substrate chip a multiplicity of gate insulator regions, each associated with a different one of the transistors and overlying a semiconductive bulk region, the gate insulator regions being disposed in respective positions in an array of intersecting rows and columns, the gate insulator regions being spaced apart, except that the gate insulator regions situated in adjacent rows within a column being adjoined to form merged gate insulator regions;

(2) forming on the chip a plurality of spaced apart gate conductor paths, each positioned to lie along a respective one of the rows and to overlie the gate insulator regions in the respective one of the rows and serving as the gate electrode where crossing a gate insulator region;

(3) forming source/drain regions in portions of the semiconductive bulk region underlying portions of the gate insulator regions not covered by a gate conductor path;

(4) forming contact means to the source/drain regions; and

(5) forming above the semiconductive bulk region a plurality of second conductor paths for interconnecting the contact means and extending generally orthogonally to the gate conductor paths.

2. A method for fabricating a random-logic IGFET integrated circuit, the circuit having a signal node, a common node, one or more branches connected from the signal node to the common node, a multiplicity of branch transistors connected in series and/or parallel combinations along the branches, each branch transistor having a gate electrode connected to one of a plurality of gate nodes, the method comprising the steps of:

(1) forming on a single substrate chip a multiplicity of gate insulator regions, each associated with a different one of the branch transistors and overlying a semiconductive bulk region, the gate insulator regions being disposed in respective positions in an array of intersecting columns and rows, at least one column corresponding to each branch and containing gate insulator regions associated with branch transistors of the corresponding branch, each row corresponding to a respective one of the gate nodes and containing gate insulator regions associated with branch transistors having gate electrodes connected to the corresponding gate node, the gate insulator regions being spaced apart, except that the gate insulator regions situated in adjacent rows within a column being adjoined to form merged gate insulator regions;

(2) forming on the chip a plurality of spaced apart gate conductor paths, each positioned to lie along a respective one of the rows and to overlie all gate insulator regions in the respective one of the rows;

(3) forming source/drain regions in portions of the semiconductive regions underlying portions of the gate insulator regions not covered by a gate conductor path;

(4) forming contact means to selected ones of the source/drain regions; and

(5) forming above the semiconductive bulk region a plurality of second conductor paths for interconnecting the contact means.

3. A method for fabricating a random-logic IGFET integrated circuit as recited in claim 2 wherein the number of columns in the array corresponding to a branch is equal to the largest number of branch transistors in the branch having gate electrodes connected to a common gate node.

4. A method for fabricating a random-logic IGFET integrated circuit as recited in claim 3 wherein the gate conductor paths are formed to be parallel and regularly spaced.