Method of making high performance bipolar transistor with polysilicon base contacts

• US 4,319,932 A
• Filed: 03/24/1980
• Issued: 03/16/1982
• Est. Priority Date: 03/24/1980
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jambotkar, Chakrapani G.
• Primary Examiner(s): Roy, Upendra
• Application Number:
  US06/133,156
• Time in Patent Office: 722 Days
• Field of Search: 148/1.5, 148/187, 29/571, 357/34, 357/59, 357/91
• US Class Current: 438/370
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/42304 Base electrodes for bipolar transistors
• CPC Class Codes: H01L 29/7325 having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor
• CPC Class Codes: Y10S 148/131 Reactive ion etching rie
• CPC Class Codes: Y10S 148/145 Shaped junctions

Abstract

Bipolar transistor devices are formed by employing polysilicon base contacts self-aligned with respect to a diffusion or ion implantation window used to form emitter, intrinsic base and raised subcollector regions. The polysilicon acts as a self-aligned impurity source to form the extrinsic base region therebelow and, after being coated with silicon dioxide on its surface and along the sidewalls of the diffusion or ion implantation window, as a mask. Directional reactive ion etching is used to form a window in the silicon dioxide while retaining it along the sidewalls. Ion implantation, for example, may be used to form, through the window, an emitter, intrinsic base and raised subcollector region. The silicon dioxide is used as an insulator to separate the emitter contact from polysilicon.

Claims

1. A process for fabricating NPN bipolar transistors having a self-aligned polysilicon base contact in close-spaced relationship to the emitter contact therefor, comprising the following sequence of steps;

forming a layer of P⁺ doped polysilicon on a substrate at least a portion of which is an N-type silicon material;

forming a layer of insulating material over said layer of P⁺ doped polysilicon;

etching said layer of insulating material and polysilicon down to said N-type material to form an opening therethrough;

forming a thin layer of insulating material on said N-type material at the bottom of said opening and along the sidewalls of said polysilicon layer exposed by said opening;

diffusing the P⁺ doping material from said polysilicon layer into said N-type silicon material to form an extrinsic base region;

etching by directional reactive ion etching the said thin layer of insulating material at the bottom of said opening as delineated by said sidewalls so as to remove the said insulating material at the bottom of said opening while leaving said insulating material on said sidewalls;

forming through said opening with insulating sidewalls an intrinsic P-type base region therebelow; and

forming through said opening with insulating sidewalls an N-type region above said intrinsic P-type base region, said N-type region forming a shallow N-type emitter.

2. The process as set forth in claim 1 wherein said insulating material is silicon dioxide formed by thermal oxidation.

3. The process as set forth in claim 2 wherein said N-type silicon material is an N^- type epitaxial layer.

4. The process as set forth in claim 3 wherein said N-type emitter region is N⁺ -type.

5. The process as set forth in claim 4 wherein the step of forming said shallow N⁺ -type emitter region includes the step of forming said emitter region by ion implantation of arsenic.

6. The process as set forth in claim 5 wherein the step of forming said intrinsic P-type base region includes the step of forming said base region by ion implantation of boron.

7. The process as set forth in claim 4 including the step of forming an N-type raised subcollector region beneath said intrinsic P-type base region.

8. The process as set forth in claim 7 wherein said N-type raised subcollector region is N⁺ -type.

9. The process as set forth in claim 8 wherein said N⁺ -type raised subcollector region is formed by the step of ion implantation of phosphorus.

10. The process as set forth in claim 6 including the further step of forming an N⁺ -type raised subcollector region beneath said intrinsic P-type base region by ion implantation of phosphorus.

11. A process for fabricating NPN bipolar transistors with a polysilicon base contact being in close-spaced and self-aligned relationship to the emitter contact therefore, comprising the following sequence of steps;

forming an N⁺ -type subcollector region in a P-type silicon substrate;

forming an N-type epitaxial layer on at least said N⁺ -type subcollector;

forming a layer of P⁺ doped polysilicon on at least said N-type epitaxial layer;

forming a layer of insulating material over said layer of P⁺ doped polysilicon;

etching said layer of insulating material and said polysilicon down to said N-type epitaxial layer to form an opening in said insulating material and said polysilicon;

forming a thin layer of insulating material on said epitaxial layer at the bottom of said opening and along the sidewalls of said polysilicon layer exposed by said opening while at the same time diffusing the said P⁺ doping material from said polysilicon layer into said N-type epitaxial layer to form an extrinsic base region;

etching by directional reactive ion etching the said thin layer of insulating material at the bottom of said opening as delineated by said sidewalls so as to remove the said insulating material at the bottom of said opening while leaving said insulating material on said sidewalls;

forming through said opening with insulating sidewalls an intrinsic P-type base region therebelow; and

forming through said opening with insulating sidewalls an N-type region above said P-type intrinsic base region, said N-type region forming a shallow N-type emitter.

12. The process as set forth in claim 11 wherein said insulating material is silicon dioxide.

13. The process as set forth in claim 12 wherein said silicon dioxide is formed by thermal oxidation.

14. The process as set forth in claim 13 wherein said P-type silicon substrate is P^- type, and said N-type epitaxial layer is N^- type.

15. The process as set forth in claim 14 wherein said N-type emitter region is N⁺ -type.

16. The process as set forth in claim 15 wherein the step of forming said N⁺ -type emitter region includes the step of forming an emitter region by ion implantation of arsenic.

17. The process as set forth in claim 16 wherein the step of forming said intrinsic P-type base region includes the step of forming a base region by ion implantation of boron.

18. The process as set forth in claim 15 including the further step of forming an N-type raised subcollector region beneath said P-type intrinsic base region and submerged partially into said N⁺ -type subcollector region.

19. The process as set forth in claim 18 wherein said N-type raised subcollector region is N⁺ -type.

20. The process as set forth in claim 19 wherein said N⁺ -type raised subcollector region is formed by the step of ion implantation of phosphorus.

21. The process as set forth in claim 17 including the further step of forming an N⁺ -type, raised subcollector region beneath said P-type intrinsic base region and submerged partially into said N⁺ -type subcollector region by ion implantation of phosphorus.

22. A process for fabricating NPN bipolar transistors having a polysilicon base contact in close-spaced and self-aligned relationship to the emitter contact therefor, comprising the following sequence of steps;

forming an N⁺ subcollector region in a P^- silicon substrate;

forming an N^- epitaxial layer on at least a portion of said N⁺ subcollector region;

forming a layer of P⁺ doped polysilicon on at least a portion of said N^- epitaxial layer;

forming a layer of insulating material over said polysilicon;

etching said layer of insulating material and polysilicon down to said epitaxial layer to form an opening therethrough;

thermally forming a thin layer of insulating material on said epitaxial layer at the bottom of said opening and along the sidewalls of said polysilicon layer exposed by said opening to form an insulating material-coated opening while at the same time diffusing the said P⁺ doping material from said polysilicon layer into said N^- epitaxial layer to form an extrinsic base region;

etching by directional reactive ion etching the said thin layer of insulating material at the bottom of said opening as delineated by the sidewalls of said coated opening so as to remove said insulating material at the bottom of said opening while leaving it on said sidewalls;

forming through said coated opening a first N region therebelow using said coated polysilicon as a mask, said first N region forming a shallow N⁺ emitter; and

forming through said coated opening an intrinsic P-type base region beneath said N⁺ emitter region using said coated polysilicon as a mask.

23. The process as set forth in claim 22 wherein said insulating material is silicon dioxide.

24. The process as set forth in claim 23 wherein said shallow N⁺ emitter and intrinsic P-type base region are formed by ion implantation.

25. The process as set forth in claim 24 wherein said ion implantation includes ion implantation of arsenic and boron.

26. The process as set forth in claim 25 including the further step of ion implantation of phosphorus to form a raised subcollector region beneath said intrinsic P-type base region and submerged partially into said N⁺ subcollector region.