Alpha-numeric-display system with selectable crawl

• US 4,320,395 A
• Filed: 03/10/1980
• Issued: 03/16/1982
• Est. Priority Date: 03/12/1979
• Status: Expired due to Term

• Current Assignee: Kernforschungsanlage Julich Gesellschaft mit beschrankter Haftung
• Original Assignee: Kernforschungsanlage Julich Gesellschaft mit beschrankter Haftung
• Inventors: Loser, Friedrich, Meissen, Ralf, Krischer, Christof, Berwix, Joachim
• Primary Examiner(s): Curtis, Marshall M.
• Application Number:
  US06/128,521
• Time in Patent Office: 736 Days
• Field of Search: 340/726, 340/724, 340/723, 340/731, 178/30, 178/15
• US Class Current: 345/685
• CPC Class Codes: G09G 5/343 for systems having a character code-mapped display memory

Abstract

A television-type system for displaying characters of an alpha-numeric testn a horizontal line moving across the face of a TV monitor includes pulse-generator-fed frequency dividers emitting pulse sequences of which three are transmitted via viewer-operated selectors for forming two frequencies f_L and f_Z applied to shift registers of a character generator to determine character height and width and another frequency f_G applied to the stepping input of a delay-increment counter to determine character speed. In response to character codes transmitted from an input unit via a read/write memory, the character generator emits binary signals combinable with horizontal and vertical sync pulses into a video signal fed to the monitor. The counter is reset upon every horizontal sync pulse to have a modulus n equal to the contents of a total-delay counter stepped by the vertical sync pulses and reset after N of the same by a divder calculating the quotient N=T_Z /T_G in response to signals from the selectors coding the periods T_Z, T_G of sequences f_Z, f_G. The delay-increment counter enables the emission of frequency f_Z only after counting n pulses of sequence f_G, whereby the character display is shifted leftwardly upon each vertical sync pulse by distance corresponding to period T_G. Upon completing N counts the total-delay counter enables its own resetting by the divider and increments an initial address of a counter addressing the read/write memory. An arithmetic unit resets the contents n of the total-delay counter upon a change in the selected sequence f_G.

Claims

1. In a method for displaying an alpha-numeric text in a horizontal line on a face of a television monitor, wherein sequential characters of said text move across said face in a fixed spatial relationship to one another, said characters being prestored in coded form and subsequently decoded into binary signals combined with horizontal and vertical sync pulses and fed to the receiving terminals of said monitor for effectuating the display of said text, signals corresponding to a first character in a horizontal scan being emitted only upon the elapse of a delay time following said horizontal sync pulses, said characters having on said face a common apparent character width correponding to a horizontal-scanning interval T_Z substantially less than an interval between consecutive horizontal sync pulses, the improvement comprising the steps of:

generating a frequency f_G which is at least equal to the reciprocal of said interval T_Z ; and

successively decreasing, upon said vertical sync pulses, said delay time by an increment T_G to implement motion of said characters across said face, said increment T_G being equal to the period of said frequency f_G and

controlling said width by application of a horizontal sampling frequency f_Z whose period is equal to said interval T_Z, said frequency f_G being an integral multiple of said sampling frequency f_Z.

2. The improvement defined in claim 1 wherein said delay time is decreased upon each of each of a plurality of consecutive vertical sync pulses to effect in the apparent location of each character a total horizontal shift corresponding to an integral multiple of said interval T_Z.

3. The improvement defined in claim 2, further comprising the steps of generating a plurality of frequencies f_G '"'"' equal to respective integral multiples of said sampling frequency f_Z and selecting one of said frequencies f_G '"'"' to serve as said frequency f_G, whereby the speed of said characters across said face may be varied.

4. The improvement defined in claim 1, 2 or 3 wherein said interval T_Z is an integral multiple of said increment T_G.

5. In a television display system, the combination comprising:

a TV monitor having a viewing face;

memory means for storing a sequence of characters of an alpha-numeric text to be displayed in a moving horizontal line on said face;

pulse-generating means for producing horizontal sync pulses, vertical sync pulses and a pulse train having a period less than the interval between consecutive horizontal sync pulses;

a character generator operatively connected to said memory means for emitting in response to signals therefrom binary pulses transmittable to said monitor in synchronous combination with said horizontal sync pulses and said vertical sync pulses for producing on said face a display of said characters;

transmission means connected to said character generator, to said pulse-generating means and to said monitor for feeding thereto said binary pulses and said horizontal sync pulses and said vertical sync pulses;

addressing means linked to said memory for sequentially reading consecutive character codes therefrom to said character generator; and

a control circuit operatively coupled to said character generator for enabling, during each horizontal scan by said monitor, the emission of said binary pulses only upon the elapse of a delay following said horizontal sync pulses, said control circuit including delay-modification means connected to said pulse-generating means for recurrently decreasing said delay upon said vertical sync pulses by an increment equal to said period, whereby said delay is changed from an upper limit to a lower limit to implement motion of said characters across said face, said control circuit further including address-incrementing means connected to said addressing means for modifying an initial address thereof upon the attainment of said lower limit by said delay and to said delay-modification means for simultaneously increasing said delay to said upper limit, wherein said characters are decoded by said character generator to have on said face a common character width corresponding to a horizontal scanning interval, said characters being generated to have a common character width corresponding to a horizontal scanning interval equal to an integral multiple of periods and wherein said lower limit is zero.

6. The combination defined in claim 5 wherein said pulse-generating means includes a high-frequency pulse generator and frequency-divider means connected thereto for feeding to said character generator a pulse sequence for enabling the emission of said binary signals to said monitor via said transmission means and for determining said width, said control circuit being operatively connected to said frequency-divider means for disabling upon said horizontal sync pulses the emission of said sequence for a time equal to said delay and for calculating, in response to a signal from said frequency-divider means coding the magnitude of said scanning interval and in response to said train, an increment count necessary to change said delay from said upper limit to said lower limit.

7. The combination defined in claim 6 wherein said frequency divider means includes a first frequency divider for determining said width and a second frequency divider for determining the speed of character motion across said face, further comprising first selector means inserted between said first frequency divider and said character generator for varying the frequency of said sequence, thereby adjusting said width, and second selector means inserted between said second frequency divider and said control circuit for varying the frequency of said train, thereby adjusting the speed of character motion.

8. The combination defined in claim 7 wherein said delay-modification means include a first counter connected at a stepping input to said pulse-generating means for changing the magnitude of said delay upon said vertical sync pulses and a second counter connected to said pulse-generating means and to said first counter for being reset upon each horizontal sync pulse to have a modulus corresponding to the contents of said first counter, said second counter being connected at a stepping input to said second selector and at an output to said first frequency divider for enabling same upon counting a number of pulses of said train equal to said modulus.

9. The combination defined in claim 8 wherein said control circuit further includes arithmetic divider means connected to said first selector, said second selector and said first counter for changing the modulus thereof in response to changes in the frequencies of said train and said sequence, thereby minimizing jumps in character movement.

10. The combination defined in claim 8 or 9 wherein said first counter has an output connected to said addressing means for incrementing an initial address thereof upon the counting of consecutive vertical sync pulses equal in number to the modulus of said first counter.