Field programmable device having test provisions for fault detection
First Claim
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1. A field programmable device having a memory array member comprising:
- a plurality of regular bit lines,a plurality of regular word lines defining cross points with said plurality of regular bit lines,regular memory cells connected at respectively associated cross points between said plurality of regular bit lines and said plurality of regular word lines,at least one test line adjacent a corresponding one of said pluralities of said regular bit lines and said regular word lines and defining cross points with the lines of the other of said pluralities of regular bit lines and regular word lines,test memory cells respectively connected at the said cross points of said at least one test line and said lines of the said other of said pluralities of regular bit lines and regular word lines,means for selectively supplying address signals of "1" and "0" levels for selecting respectively corresponding ones of said lines of the said other of said pluralities of regular bit lines and regular word lines, andsaid test memory cells comprising non-conductive test memory cells connected at the said cross points with said corresponding lines of the said other of said pluralities of said regular bit and said regular word lines selected by a "0" level address signal, and conductive test memory cells connected at the cross points with said lines of the said other of said pluralities of said regular bit and said regular word lines selected by a "1" level address signal.
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Abstract
A field programmable device having a memory cell member including regular bit lines, regular word lines, regular memory cells connected at the cross points of said regular bit lines and regular word lines, test bit or test word lines, and non-conductive and conductive test memory cells connected at the cross points of said regular bit or regular word lines and test word or test bit lines, wherein the conductivity of a test memory cell is determined by the "1" or "0" of the address signal by which the test word or test bit line to which the test memory cell is connected is selected.
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Citations
7 Claims
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1. A field programmable device having a memory array member comprising:
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a plurality of regular bit lines, a plurality of regular word lines defining cross points with said plurality of regular bit lines, regular memory cells connected at respectively associated cross points between said plurality of regular bit lines and said plurality of regular word lines, at least one test line adjacent a corresponding one of said pluralities of said regular bit lines and said regular word lines and defining cross points with the lines of the other of said pluralities of regular bit lines and regular word lines, test memory cells respectively connected at the said cross points of said at least one test line and said lines of the said other of said pluralities of regular bit lines and regular word lines, means for selectively supplying address signals of "1" and "0" levels for selecting respectively corresponding ones of said lines of the said other of said pluralities of regular bit lines and regular word lines, and said test memory cells comprising non-conductive test memory cells connected at the said cross points with said corresponding lines of the said other of said pluralities of said regular bit and said regular word lines selected by a "0" level address signal, and conductive test memory cells connected at the cross points with said lines of the said other of said pluralities of said regular bit and said regular word lines selected by a "1" level address signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification