Cell capacity detector

• US 4,321,541 A
• Filed: 12/03/1979
• Issued: 03/23/1982
• Est. Priority Date: 12/04/1978
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Inventors: Nishizuka, Akihiro
• Primary Examiner(s): Tokar, Michael J.
• Application Number:
  US06/099,746
• Time in Patent Office: 841 Days
• Field of Search: 324/429, 324/427, 324/430, 324/426
• US Class Current: 324/426
• CPC Class Codes: G01R 31/36 Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
• CPC Class Codes: G01R 31/3648 comprising digital calculation means, e.g. for performing an algorithm
• CPC Class Codes: G01R 31/386 using test-loads
• CPC Class Codes: G04C 10/04 with means for indicating the condition of the power supply in general G01R31/36

Abstract

A capacity detector of a cell used as a source of power for a watch, camera or any other portable implement, wherein a resistive load is connected in series through a switch; the switch is opened immediately after a prescribed length of time; a speed of the cell voltage restoration is calculated which is required for a cell voltage restored after the opening of the switch to be brought back to a prescribed reference level; and the remaining capacity of the cell is numerically determined from said calculated length of time.

Claims

1. A detector for determining the capacity of a cell, said detector comprising:

(a) load means;

(b) switch means between said cell and said load means for connecting and disconnecting said cell from said load means, the connection of said cell to said load means causing said cell voltage to drop; and

(c) means to measure the time for the voltage of said cell to recover from said dropped cell voltage after said disconnection of said cell from said load means.

2. A detector for determining the capacity of a cell, said detector comprising:

(a) load means;

(b) switch means between said cell and said load means for connecting and then disconnecting said cell from said load means, the connection of said load means to said cell causing said cell voltage to drop;

(c) means connected to said cell for detecting when said cell voltage equals a preset reference level after said switch means disconnects said cell from said load means; and

(d) means connected to said detecting means for determining the restoration time of said cell by measuring the time between the disconnection of said cell from said load means by said switch means and the moment when said detecting means first indicates that said cell voltage equals said preset reference level.

3. The cell capacity detector in claim 2 wherein said restoration time determining means further comprises:

(a) a clock pulse generator producing a series of clock pulses; and

(b) a counter for counting the clock pulse generator pulses in response to signals from said detector means and said switch means.

4. The cell capacity detector in claim 3 wherein said restoration time determining means includes means to count said clock pulses issued by a said clock pulse generator only after said detecting means indicates that said cell voltage equals said preset reference voltage.

5. The cell capacity detector in claim 2 or 4 further comprising display means connected to said restoration time determining means for indicating a capacity of said cell.

6. The cell capacity detector in claim 2 further comprising means for periodically activating said switch means to begin said cell capacity detection and means for storing the results from said restoration time determining means until the next activation of said switch means.

7. The cell capacity detector in claim 5 further comprising means for periodically activating said switch means to begin said cell capacity detection and means, connected to said display means, for storing the results from said restoration time determining means until the next activation of said switch means.

8. The cell capacity detector of claim 2, wherein said detecting means further comprises:

(a) inverter circuit means connected across the positive and negative terminals of said cell, the output of said inverter circuit indicating the relationship between said cell voltage and said preset reference voltage; and

(b) a bias circuit connected across said cell terminals, the output of said bias circuit being connected to the input of said inverter circuit means, said bias circuit generating a signal to indicate whether said cell voltage is equal to said preset voltage.

9. The cell capacity detector in claim 8 wherein said detecting means further comprises a power saving circuit connected in parallel with said cell, said power saving circuit including an output terminal connected to an input of said bias circuit and including:

(a) a first transistor having a source connected to one terminal of said cell and having a gate connected to said restoration voltage determining means;

(b) resistance means having two end terminals and an intermediate terminal, one of said end terminals being connected to the drain of said first transistor and said intermediate terminal being connected to said output terminal of said power saving circuits; and

(c) a second transistor having its gate and drain connected to the other end terminal of said resistance means and having a source connected to the other terminal of said cell.

10. The cell capacity detector of claim 8 or 9 further comprising means for generating a binary signal in response to the output of said inverter circuit means to indicate the relationship between said cell voltage and said preset reference voltage.