High speed serial access semiconductor memory with fault tolerant feature

• US 4,321,695 A
• Filed: 11/23/1979
• Issued: 03/23/1982
• Est. Priority Date: 11/23/1979
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Redwine, Donald J., White, Lionel S. Jr.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/097,106
• Time in Patent Office: 851 Days
• Field of Search: 365/240, 365/174, 365/189, 365/200, 365/222, 365/182, 365/185, 307/238
• US Class Current: 365/200
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1036 using data shift registers
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter

Abstract

A semiconductor memory device of the single-chip MOS/LSI one-transistor dynamic RAM cell array type stores both data and address in rows of the array and uses a high speed serial access shift register as its data input/output system. The serial shift register has a number of stages equal to the number of columns in the memory cell array, and data in the shift register is transferred into or out of the columns of the array when a comparator indicates that an address input matches the stored row address. The rows are sequentially activated by a commutator, so no row or column decoders are needed. The device may be made fault tolerant by use of an electrically programmable floating gate transistor connected to each row, and programming this transistor to blank input or output if the row includes bad cells. The fault tolerant feature is transparent to the computer system using the memory.

Claims

1. A memory device comprising an array of rows and columns of memory cells formed in a face of a semiconductor body, the major part of said array being a data memory and a minor part of the array being an address memory, a commutator for sequentially addressing said rows one at a time and means for reading out address and data from columns when a row is addressed, a serial access register connected via transfer means to the means for reading out to receive data from columns of said array, address input means in said face and connected to receive a multibit address from external to the device, comparator means in said face responsive to an address in said address input means and to said means for reading out and producing a command when the address from external is the same as the address from the array, means to activate said transfer means for the serial access register in response to said command, and output means for reading said data from the serial access register to external to the device.

2. A memory device according to claim 1 wherein said memory cells are read/write cells of the one-transistor dynamic type.

3. A memory device according to claim 2 wherein means are provided for writing data into said serial access register from external to the device.

4. A memory device according to claim 3 wherein means are provided for inserting said multibit address from the address input means into said address memory part of the array in response to said command.

5. A memory device according to claim 4 wherein the means for reading out includes a bistable differential sense amplifier at the center of each column of the array.

6. A memory device according to claim 5 including means for actuating said sense amplifiers for refresh in response to sequential addressing of the rows by said commutator.

7. A memory device according to claim 1 wherein the data memory part of the array includes M rows and N columns, the serial access register includes N stages, and the address memory part of the array includes M rows, when M and N are integral powers of two.

8. A memory device comprising an array of rows and columns of memory cells formed in a face of a semiconductor body, the major part of said array being a data memory and a minor part of the array being an address memory, a commutator for sequentially addressing said rows one at a time and means for reading out address and data from columns when a row is addressed, a serial access register connected via transfer means to the means for reading out to receive data from columns of said array, address input means in said face and connected to receive a multibit address from external to the device, comparator means in said face responsive to an address at said address input means and to said means for reading out and producing a command when the address from external is the same as the address from the array, means to activate said transfer means for the serial access register in response to said command, output means for reading said data from the serial access register to external to the device, a programmable transistor connected to each row and coupled to blanking means, and means to program such transistor if one or more cells in such row test bad.

9. A memory device according to claim 8 including means for inhibiting the storage of data and address in memory cells of a row in response to said blanking means.

10. A memory device according to claim 9 wherein each said programmable transistor is a floating gate electrically-programmable MOS transistor, and means are included on said face for applying a programming voltage to the source-to-drain path of the MOS transistors when said commutator addresses a row which includes one or more bad cells.

11. A memory device comprising an array of rows and columns of memory cells formed in a face of a semiconductor body, the major part of said array being a data memory and a minor part of the array being an address memory, means for addressing said rows one at a time and output means for reading out address and data from columns when a row is addressed, an access register connected via transfer means to said output means to receive data from columns of said array, address input means in said face and connected to receive a multibit address from external to the device, comparator means in said face responsive to an address at said address input means and to said output means and producing a command when the address from external is the same as the address from the array via said output means, means to activate said transfer means for the access register in response to said command, and means for reading said data from the access register to external to the device.

12. A memory device according to claim 11 wherein said memory cells are read/write cells of the one-transistor dynamic type.

13. A memory device according to claim 12 wherein means are provided for writing data into said serial access register from external to the device.

14. A memory device according to claim 13 wherein means are provided for inserting said multibit address from the address input means into said address memory part of the array.

15. A memory device according to claim 13 wherein the output means includes a bistable differential sense amplifier at the center of each column of the array.

16. A memory device according to claim 15 including means for actuating said sense amplifiers for refresh in response to sequential addressing of the rows by said commutator.

17. A memory device according to claim 11 wherein the data memory part of the array includes M rows and N columns, the access register includes N stages, and the address memory part of the array includes M rows, when M and N are integral powers of two.

18. A memory device according to claim 11 including a programmable device connected to each row and coupled to blanking means, and means to program such programmable device if one or more cells in such row test bad.

19. A memory device according to claim 18 including means for inhibiting the storage of data and address in memory cells of a row in response to said blanking means.

20. A memory device according to claim 19 wherein each said programmable device is a floating gate electrically-programmable MOS transistor, and means are included on said face for applying a programing voltage to the source-to-drain path of the MOS transistors when said commutator addresses a row which includes one or more bad cells.

21. A memory device comprising an array of rows and columns of memory cells formed in a face of semiconductor body, means for addressing said rows one at a time and output means for reading out data from columns when a row is addressed, an access register connected via transfer means to the output to receive data from columns of said array, address input means in said face and connected to receive a multibit address from external to the device, means in said face responsive to an address in said address input means and producing a command when the address from external is of predetermined character, means to activate said transfer means for the access register in response to said command, and means for reading said data from the access register to external to the device programmble means connected to each row and coupled to blanking means, and means to program said programmable means if one or more cells in a row test bad.

22. A memory device according to claim 21 including means for inhibiting the storage of data in memory cells of a row in response to said blanking means.

23. A memory device according to claim 22 wherein each said programmable device is a floating gate electrically-programmable MOS transistor, and means are included on said face for applying a programming voltage to the source-to-drain path of the MOS transistors.