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High speed serial shift register for MOS integrated circuit

  • US 4,322,635 A
  • Filed: 11/23/1979
  • Issued: 03/30/1982
  • Est. Priority Date: 11/23/1979
  • Status: Expired due to Term
First Claim
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1. In a dynamic shift register having first and second driver transistors, first and second precharge transistors, and first and second transfer transistors in each stage, each such transistor having a source-drain path and a gate, the source-drain paths of the first driver and first precharge transistors being connected together at a first node and in series between first grounding means and a voltage supply, the source-drain paths of the second driver and second precharge transistors being connected together at a second node and in series between second grounding means and said voltage supply, the source-drain path of the first transfer transistor connecting said first node to the gate of the second driver transistor, the source-drain path of the second transfer transistor connecting said second node to an output node for the stage, the gate of the first driver transistor being an input node for the stage, and four different clock voltage sources connected separately to the gates of the first and second precharge transistors and the first and second transfer transistors, the improvement wherein:

  • the four clock voltage sources include a first clock having an on time during a first interval and connected to the gate of the first precharge transistor, a second clock having an on time during said first interval plus a succeeding second interval and connected to the gate of the first transfer transistor, a third clock having an on time during a third interval not overlapping the first or second intervals and delayed in time from the end of the second interval, the third clock being connected to the gate of the second precharge transistor, and a fourth clock having an on time during said third interval plus a succeeding fourth interval and connected to the gate of the second transfer transistor.

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