Monitoring device for the capacitor battery of a d-c filter circuit

• US 4,322,766 A
• Filed: 07/03/1980
• Issued: 03/30/1982
• Est. Priority Date: 07/24/1979
• Status: Expired due to Term

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Becker, Michael, Renz, Klaus, Weibelzahl, Manfred
• Primary Examiner(s): Salce, Patrick R.
• Application Number:
  US06/165,754
• Time in Patent Office: 635 Days
• Field of Search: 361/15, 361/16, 361/17, 361/87, 361/86, 361/113, 361/78, 324/51, 324/60 R, 324/60 C, 340/635
• US Class Current: 361/17
• CPC Class Codes: G01R 31/64 Testing of capacitors
• CPC Class Codes: H02H 7/16 for capacitors for synchronous capacitors H02H7/06

Abstract

A circuit for monitoring the capacitor battery of a filter circuit connected to a transmission line, the capacitor battery consisting of at least two parallel legs, each with a number of series-connected capacitors. A first signal is produced which corresponds to the total alternating current flowing through the capacitor battery. A second signal is produced which corresponds to the difference between the currents flowing through the respective parallel legs of the capacitor battery. The current difference signal is compared with a respective fraction of the total current signal. A fault indicator signal is produced if the difference between the difference current signal and the fractional total current signal exceeds a predetermined threshold value. Further circuitry is provided for correcting drift in the difference current signal, which may be caused by temperature variations or acceptable capacitor failures. Automatic ranging circuitry may be provided in embodiments of the invention in which the total capacitor battery current varies in amplitude over a large range.

Claims

1. A circuit for monitoring the capacitor battery of a filter circuit connected to a transmission line, the capacitor battery being composed of a multiplicity of individual capacitors which are arranged in at least two similar parallel legs, each leg having a plurality of capacitors connected in series, characterized in that there are provided:

a. means for producing a first signal which is responsive to the total alternating current flowing through the capacitor battery,

b. means for producing a second signal which is responsive to the difference between the alternating currents flowing through the parallel legs of the capacitor battery,

c. means for producing at least one third signal which is responsive to the difference between a predetermined fraction of said first signal, and said second signal, and

d. means responsive to said third signal for producing a fault indication signal if the amplitude of said third signal exceeds a predetermined threshold value.

2. The circuit of claim 1 in which there is further provided drift correction circuitry for compensating for unequal currents flowing through the parallel legs of the capacitor battery, the drift correction circuitry comprising:

a. mixer means having a first input terminal for receiving said second signal, a second input terminal for receiving a correction signal, and an output terminal for providing a signal corresponding to the sum of the signals at said first and second input terminals,

b. inverter means having an input terminal connected to the output terminal of said mixer means and an output terminal for providing a signal corresponding to the polarity-inverted output signal of said mixer means,

c. first multiplier means having a first input terminal for receiving said first signal, a second input terminal connected to the output terminal of said inverter means, for receiving said inverted signals from the output terminal of said mixer means, and an output terminal for producing a signal corresponding to the product of the signals at said first and second input terminals,

d. integrating means having an input terminal for receiving the signal at the output terminal of said first multiplier means, and an output terminal for providing a signal corresponding to an integration of the signal at said input terminal, over a predetermined integration time constant, which output signal corresponds to the degree of inequality between the currents flowing through the parallel legs of the capacitor battery, and

e. second multiplier means having a first input terminal for receiving said first signal, a second input terminal connected to the output terminal of said integrating means, and an output terminal connected to said second input terminal of said mixer means for providing a correction signal.

3. The circuit of claim 1 in which there is further provided:

a. first amplifier means having adjustable gain, for amplifying said first signal,

b. second amplifier means having adjustable gain, for amplifying said second signal, and

c. means for adjusting the gains of said first and second amplifier means in response to the amplitude of said first signal.

4. The circuit of claim 1 in which there is further provided n-1 means for producing n-1 additional third signals, each of the n third signals being responsive to a respective predetermined fraction of said first signal, the circuit further comprising:

a. n limiter means, each having a predetermined response threshold, an input terminal for receiving a respectively associated one of said n third signals, and an output terminal for providing a standardized output signal when the respectively associated ones of said n third signals exceeds the predetermined response threshold,

b. first summer means having n input terminals, each connected to a respectively associated output terminal of said n limiter means, and an output terminal for providing a signal responsive to the sum of the output signals of said n limiter means,

c. n time circuits, each having a predetermined response delay interval, an input terminal connected to a respectively associated one of said n limiter means, and an output terminal for providing a standardized output signal in response to the standardized output signal of the respectively associated one of said n limiter means and the response delay interval,

d. second summer means having n input terminals each connected to a respectively associated one of the output terminals of said n time delay circuits, and an output terminal for providing a signal responsive to the sum of the output signals of said n time delay circuits, and

e. evaluation means for providing a fault indication signal if the difference between the output signals of said first and second summer means exceeds a predetermined level.