High performance semiconductor package assembly

• US 4,322,778 A
• Filed: 01/25/1980
• Issued: 03/30/1982
• Est. Priority Date: 01/25/1980
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Magdo, Steven, Lemke, Guido A., Barbour, Donald R.
• Primary Examiner(s): JAMES, ANDREW
• Application Number:
  US06/115,580
• Time in Patent Office: 795 Days
• Field of Search: 174/68.5, 361/414, 361/412, 357/80, 357/70, 357/74, 333/1, 333/346, 333/347, 333/348
• US Class Current: 361/794
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

An improved high performance semiconductor package assembly for interconnecting a plurality of integrated circuit devices having a multilayer substrate with internal wiring including signal wiring and external signal and power connections, a plurality of integrated circuit semiconductor devices supported on the top surface of substrate in electrically connected operative relation, the improvement being a power supply distribution system for providing electrical supply voltages to the devices from the power connections consisting of radial waveguide structure including parallel waveguide planes with a low input impedence to reduce switching noise, the waveguide planes located between the signal fan-out wiring and internal wiring metallurgy and connected in common to all of the plurality of devices.

Claims

1. A package assembly for interconnecting a plurality of integrated circuit semiconductor devices having a multi-layer dielectric material substrate with a signal fan-out wiring pattern and internal wiring metallurgy interconnecting the semiconductor devices, a plurality of integrated circuit semiconductor devices supported on the top surface of the substrate in electrically connected operative relation, and external signal and power connection means, the improvement comprising

a power supply distribution system for connecting electrical supply voltages to said devices from power connection means comprised of radial waveguide structure with parallel waveguide planes with a low input impedence, said waveguide planes located between said signal fan-out wiring pattern and the said internal wiring metallurgy in said substrate, vertical vias connecting said waveguide planes to said devices and external connection means, said waveguide planes connected in common to all of said plurality of devices.

2. The package assembly of claim 1 wherein said dielectric material of said substrate is ceramic material.

3. The package assembly of claim 1 wherein said dielectric material of said substrate is a polymerized organic resin material.

4. The package assembly of claim 1 wherein said vertical vias was interspersed between signal vias which provide vertical interconnections for said signal wiring planes.

5. The package assembly of claim 4 wherein the input impedance of said radial waveguide structure is less than 0.2 ohms.

6. The package assembly of claim 5 wherein the vertical distance between said devices on the top surface of said substrate and said waveguide planes is less than 60 mils.

7. The package assembly of claim 6 wherein said substrate further includes power planes positioned between sets of X and Y signal wiring planes, and vias interconnecting said waveguide planes with said power planes.

8. The package assembly of claim 1 wherein the substrate includes multilayer ceramic interposers and a base, said interposers mounted on said base, each interposer having at least one cluster of solder pads on the top surface, at least one semiconductor device operatively mounted on said cluster of solder pads, a decoupling capacitor on the bottom side comprised of a plurality of said parallel waveguide planes, power vias connecting said waveguide planes to said power connection means on said base.

9. The package assembly of claim 8 wherein a plurality of interposers are provided in the package assembly, and the respective parallel waveguide planes in said interposers are interconnected with said power connection means by vias and solder pad connections on the surace of said base.

10. The package assembly of claim 9 wherein a plurality of devices are mounted on each of said interposers.

11. The package assembly of claim 8 wherein said waveguide planes on said interposers are comprised of substantially solid layers of a metal selected from the group consisting of Al and Ta, said waveguide planes separated from each other by a dielectric layer formed of oxidized metal of said waveguide planes.

12. The package assembly of claim 8 which includes a surface fan out metallurgy pattern connected to said cluster of solder pads, and a solid internal conductor plane within said interposer in close proximity to said fan out metallurgy layer.

13. The package assembly of claim 8 wherein signal vias are interspersed between said vertical power vias in said base.

14. The package assembly of claim 13 wherein the input impedance of said radial waveguide structure is less than 0.2 ohms.

15. The package assembly of claim 12 which further includes engineering change pads including surface deletable links associated with said fan-out metallurgy pattern.

16. The package assembly of claim 1 wherein said waveguide planes are metal metallurgy layers disposed in said substrate in close proximity to the surface, device power vias extending from said waveguide planes to the substrate surface to selected pads in said pad cluster, discrete capacitor elements mounted on the top surface of said substrate, and capacitor vias extending from said waveguide planes to said capacitor elements.

17. The package assembly of claim 16 wherein said capacitor elements have a plurality of metal layers corresponding to said waveguide planes, and said capacitor vias connect corresponding waveguide planes with corresponding layers in said capacitor elements.

18. The package assembly of claim 17 which includes a plurality of engineering change pads on the surface of said substrate in surrounding relation to each device mounted thereon, said engineering change pads connected to said cluster of solder pads, said capacitor elements mounted in close proximity to said devices in diagonal relation of each corner thereof.

19. The package assembly of claim 18 wherein the electrical connections between said cluster of solder pads and said engineering pads are internal metallurgy lines in said substrate adjacent the top surface and above said waveguide planes.

20. The package assembly of claim 17 wherein said metal layers and the corresponding waveguide planes are interconnected with spaced power vias that are interspersed with signal line vias.