Memory system having servo compensation

• US 4,322,819 A
• Filed: 03/23/1978
• Issued: 03/30/1982
• Est. Priority Date: 07/22/1974
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Hecker, Stuart N.
• Application Number:
  US05/889,301
• Time in Patent Office: 1,468 Days
• Field of Search: 365/103, 365/104, 365/45, 365/183, 365/222, 179/1 J, 357/24
• US Class Current: 365/45
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G10L 19/00 Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 13/04 : using optical elements ; using other beam accessed elements, e.g. electron or ion beam
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/16 : Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

The present invention is directed to a servo system for compensation of memory signals. In a preferred embodiment, the memory system is a CCD analog read only memory system. In alternate embodiments, the memory system may include an alterable memory, a bubble memory, and/or other memories. Adaptive servo compensation is provided by storing reference signals and compensating stored information signals with the stored reference signals using a compensation servo arrangement. The servo may be an implicit servo for compensating signal amplitude such as to correct charge transfer errors in a CCD memory.

Claims

1. A memory system comprising:

an analog memory for storing analog signals;

an input circuit for storing the analog signals in said analog memory at a first data rate;

an output circuit for outputting the analog signals from said analog memory at a second data rate that is lower than said first data rate;

a servo for generating refreshed output analog signals in response to the analog signals output with said output circuit; and

an analog to digital converter for generating digital output signals in response to the refreshed output analog signals generated with said servo.

2. The system as set forth in claim 1 above, wherein said memory includes means for storing the analog signals as analog magnetic signals.

3. The system as set forth in claim 1 above, wherein said servo includes means for generating the refreshed signals as a digital signal.

4. The system as set forth in claim 1 above, wherein said memory includes means for storing the analog signals as acoustical analog signals.

5. The system as set forth in claim 1 above, wherein said analog memory includes a charge coupled device for storing the analog signals;

said charge coupled device including a clock circuit for shifting the analog signals, wherein said clock circuit includes means for shifting the analog signals stored in said analog memory at the first data rate for storing the analog signals and means for shifting the analog signals stored in said analog memory at the second data rate for outputting the analog signals.

6. The system as set forth in claim 1 above, wherein said servo includes a digital to analog converter for correcting a scale factor related error in the stored analog signals.

7. The system as set forth in claim 6 above, wherein said servo further includes means for providing bias compensation to reduce bias related errors in said refreshed signal.

8. The system as set forth in claim 1 above, wherein said servo includes a comparator for generating a comparison signal related to a comparison between a reference signal and the stored analog signals;

said system further comprising a digital computer for generating the reference signal.

9. The system as set forth in claim 1 above, wherein said servo includes scale factor means for generating a scale factor compensated signal in response to the stored analog signals and bias means for generating a bias compensated refreshed signal in response to the scale factor compensated signal.

10. The system as set forth in claim 1 above, wherein said servo includes bias means for generating a bias compensated signal in response to the stored analog signals and scale factor means for generating a scale factor compensated signal in response to the bias compensated signal.

11. The system as set forth in claim 1 above, further comprising a plurality of said servos distributed at a plurality of locations in said memory.

12. The system as set forth in claim 1 above, wherein said servo includes means for generating the refreshed signals having a reduced non-linearality in response to the stored signals.

13. The system as set forth in claim 1 above, wherein said servo includes an implicit servo for generating an inverse function, wherein said implicit servo includes means for compensating the refreshed signal in response to the stored electrical signals.

14. The system as set forth in claim 1 above, further comprising monolithic means for combining said memory and said servo on a common monolithic structure.

15. The system as set forth in claim 1 above, wherein said servo includes means for compensating at least three types of errors.

16. The system as set forth in claim 15 above, wherein two of said at least three types of errors are a bias error and a scale factor error.

17. The system as set forth in claim 1 above, wherein said servo includes means for controlling gain of an electronic circuit.

18. The system as set forth in claim 1 above, wherein said servo includes gain control means for controlling scale factor of the refreshed signal and bias means for controlling bias of the refreshed signal.

19. The system as set forth in claim 1 above, wherein said memory includes an analog read only memory.

20. A memory system comprising:

a memory for storing signals and

a plurality of servos for refreshing the signals stored in said memory, wherein said plurality of servos includes a first plurality of bias refresh circuits for bias compensating signals stored in said memory and a second plurality of scale factor refresh circuits for scale factor compensating signals stored in said memory.

21. The system as set forth in claim 20 above, where the first plurality represents a greater quantity than the second plurality.

22. The system as set forth in claim 20 above, wherein the second plurality represents a greater quantity than the first plurality.

23. A memory system comprising:

a digital computer for processing digital information;

a digital to analog converter for generating an analog information signal in response to digital information processed with said digital computer;

an analog memory for storing analog information generated with said digital to analog converter; and

a servo for refreshing the analog information stored in said analog memory.

24. A reverberation system comprising:

a memory for storing electrical signals;

a servo for generating a refreshed signal in response to electrical signals stored in said memory; and

reverberation means for providing reverberation in response to the refreshed signal.

27. The system as set forth in claim 24 above, wherein said rate means includes means for providing a higher refresh rate than output rate.

25. A memory system comprising:

a memory for storing electrical signals and

a servo for generating a refreshed signal in response to electrical signals stored in said memory, wherein said servo includes a differential circuit for providing a differential signal in response to an electrical signal stored in said memory to generate a refreshed signal having reduced differential error.

26. A memory system comprising:

an analog memory for storing analog signals;

an analog refresh circuit for refreshing the analog signals stored in said analog memory at a refresh rate;

an analog output circuit for outputting the analog signals stored in said analog memory at an output rate; and

a rate circuit for controlling signal rates;

wherein said rate circuit includes

a. refresh rate means for generating a refresh rate to control said analog refresh circuit and

b. output rate means for generating an output rate to control said analog output circuit, wherein the refresh rate is different from the output rate.

28. A memory system comprising:

an analog memory for storing analog signals;

a refresh circuit for refreshing the analog signals stored in said analog memory, wherein said refresh circuit includes a differential amplifier for bias refreshing the analog signals stored in said analog memory and a transistor connected in a common leg of said differential amplifier for scale factor refreshing the analog signals stored in said analog memory.

29. A memory system comprising:

a memory for storing signals;

a reference circuit for generating a reference signal;

a comparator for generating a comparison signal in response to a comparison of the stored signals from said memory and the reference signal from said reference circuit.

30. The system as set forth in claim 29 above, wherein said comparator means includes an impliit servo for providing compensation of the signals stored in said memory.

31. The system as set forth in claim 29 above, wherein said memory is an analog CCD read only memory for storing the signals as analog charge signals in read only memory form, wherein said reference circuit includes means for generating the reference signal as an analog reference signal related to a desired signal in said memory;

and wherein said comparison means includes an analog comparator for generating the comparison signal as an analog comparison signal in response to a comparison of the analog reference signal from said reference signal generating means and at least one of the analog signals stored in said memory.

32. An analog memory system comprising:

reference input means for generating an analog reference signal;

memory storing means for storing an analog signal; and

memory output means for generating an analog memory output signal in response to a comparison between the analog signal stored in said memory storing means and the analog reference signal generated with said reference input means.

33. A memory system comprising:

an analog memory for storing analog signals

a reference circuit for generating a reference signal;

a comparator for comparing the analog signals stored in said analog memory with the reference signal generated with said reference circuit; and

an analog to digital converter for converting analog signals stored in said analog memory to digital output signals in response to a comparison between the analog signals stored in said analog memory and the reference signal generated with said reference circuit determined by said comparator.

34. The system as set forth in claim 33 above, wherein said memory includes an analog read only memory.

35. A memory system for storing electrical signals;

said memory system comprising;

memory means for storing a plurality of analog signals as stored electrical analog signals;

shifting means for shifting the stored electrical analog signals;

analog data refresh means for processing the electrical analog signals from said shifting means, said analog data refresh means including reference means for generating an analog reference signals and a servo for processing the electrical analog signals from said shifting means in response to the analog reference signals and

analog-to-digital converter means for generating digital output signals in response to the processed electrical analog signals from said analog data refresh means.