Method of fabricating MOS field effect transistors

• US 4,324,038 A
• Filed: 11/24/1980
• Issued: 04/13/1982
• Est. Priority Date: 11/24/1980
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Inventors: Murarka, Shyam P., Kahng, Dawon, Cooper, James A. Jr., Chang, Chuan C.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/209,755
• Time in Patent Office: 505 Days
• Field of Search: 29/571, 29/591, 148/187, 357/23.65
• US Class Current: 438/282
• CPC Class Codes: H01L 21/28537 Deposition of Schottky electrodes
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66643 with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact

Abstract

A method for making a MOSFET device (20) in a semiconductor body (10) includes the step of forming source and drain contact electrodes (12.1, 12.2) prior to growth of the gate oxide (10.3) and after formation of a high conductivity surface region (10.5). The exposed mutually opposing sidewall edges of each of the contact electrodes (12.1, 12.2) are coated with a sidewall silicon dioxide layer (15.1, 15.2), and the then exposed surface of the semiconductor body (10) between these sidewalls is etched to depth beneath the high conductivity surface region (10.5) in order to separate it into the source and drain regions (10.1, 10.2).

Formation of the high conductivity region may be omitted by using Schottky barrier or impurity doped material for the contact electrodes (12.1, 12.2).

Claims

1. A method of fabricating a semiconductor device (20) having a pair of spaced-apart source and drain contact electrodes (12.1, 12.2) contacting spaced-apart surface areas of source and drain regions (10.1, 10.2), respectively, located at a top surface of a semiconductor body (10) and having a gate oxide layer (10.3) grown on a first portion of the said top surface located between said apart areas characterized by the step of forming a sidewall insulating layer (15.1, 15.2) on an exposed mutually opposing sidewall edge surface of each of the contact electrodes (12.1, 12.2), followed by the step of thermally growing the gate oxide layer (10.3).

2. The method of claim 1 further characterized by the step of forming an intermediate insulating layer (13, 14) on an exposed top surface of the contact electrodes (12.1, 12.2), followed by the step of forming each said sidewall insulating layer (15.1, 15.2) by depositing an insulating layer (15) on exposed portions of the top surface of the body (10) located between said spaced-apart surface areas, on each said mutually opposing sidewall edge surface, on an exposed top surface of the intermediate insulating layer (13, 14), and on at least one other sidewall edge surface (22.1, 22.2) of each of the contact electrodes (12.1, 12.2) and followed by anisotropic etching of said insulating layer (15) whereby material of said insulating layer (15) remains on each of said mutually opposing sidewall edge surfaces to form each said sidewall insulating layer (15.1, 15.2) but does not remain on said top surfaces.

3. The method of claim 1 or 2 further characterized in that said contact electrodes (12.1, 12.2) are essentially metal-silicide, silicon rich metal-silicide, or metal.

4. The method of claim 3 further characterized by the step of depositing an electrode layer (16) extending over both said gate oxide layer (10.3) and each said sidewall insulating layer (15.1, 15.2).

5. A method for making a MOSFET device (20) comprising the steps of:

(a) forming a pair of spaced-apart contact electrodes (12.1, 12.2) whose top surfaces are coated with an intermediate insulating layer (13,

     14), said electrodes (12.1, 12.2) being essentially metal, metal-silicide, or silicon rich metal-silicide, and said electrodes making contact with spaced-apart areas of a top surface of a semiconductor body (10);

(b) forming sidewall edge insulating layers (15.1, 15.2) on exposed mutually opposed sidewall edges of each of said contact electrodes (12.1, 12.2) contiguous with said spaced-apart areas of contact;

(c) forming a recess in the body (10) at the top surface thereof located between said sidewall insulating layers (15.1, 15.2) to at least a predetermined depth;

(d) forming a gate oxide layer (10.3) coating said recess; and

(e) forming a gate electrode layer (16.3) covering both said gate oxide layer (10.3) and each of the sidewall insulating layers (15.1, 15.2).

6. The method of claim 5 in which each said sidewall insulating layer (15.1, 15.2) is formed by deposition of an insulating layer (15) on exposed portions of the top surface of the body (10) located between said contact electrodes (12.1, 12.2) on each said mutually opposing sidewall edge, on an exposed surface of the intermediate insulating layer (13, 14), and on at least one other sidewall edge surface (22.1, 22.2) of each of the contact electrodes (12.1, 12.2), followed by anisotropic etching to remove said insulating layer (15) from said top surfaces but not from any of said edge surfaces of the electrode (12.1, 12.2).

7. The method of claim 6 in which the semiconductor body (10) is single crystal silicon, the insulating layer (15) is silicon dioxide, and the gate oxide layer (10.3) is formed by thermal oxidation growth.

8. The method of claim 7 in which the gate electrode layer (16.3) is polycrystalline silicon.

9. The method of claim 6 in which said gate electrode layer (16.3) is formed by a process comprising depositing a polycrystalline silicon layer (16) simultaneously on said sidewall edge insulating layers (15.1, 15.2) and on said gate oxide layer (10.3).

10. The method of claim 6 in which impurities of opposite conductivity type from that of the bulk of the body (10) are introduced into the body (10) to form a doped region (10.5) of predetermined depth contiguous with the top surface of the body (10) between field oxide layer portions (11) prior to depositing a contact electrode layer (12) on said doped region (10.5), and then patterning said electrode layer (12) to form said spaced-apart electrodes (12.1, 12.2) thereby exposing a portion of said doped region (10.5) co-centered with the recess, the predetermined depth of said recess being greater than that of the region (10.5).

11. The method of claim 5, 6 or 10 in which the intermediate insulating layer comprises a layer (13) of silicon dioxide.

12. The method of claim 10 in which said depth of the recess is greater than said depth of the doped region (10.5) by a factor of about 1.5 or more.

13. The method of claim 11 in which the intermediate insulating layer further comprises a layer (14) of silicon nitride on the layer (13) of silicon dioxide.

14. The method of claim 6 in which at least a portion of each said other exposed sidewall edge surface (22.1, 22.2) is located where said other edge surface is contiguous with a field oxide layer portion (11) intervening between each said other edge (22.1, 22.2) and the top surface of the body (10).

15. The method of claim 6 or 14 in which the body (10) is single crystal silicon, said intermediate insulating layer (13, 14) comprises a first intermediate layer (13) of silicon dioxide covered with a second intermediate layer (14) of chemical composition different from silicon dioxide, and the gate oxide layer (10.3) is formed by thermal oxidation growth.

16. The method of claim 14 in which said gate electrode layer (16.3) is formed by the step of depositing a layer of material of said gate electrode (16.3) as a continuous electrode layer (16) extending over both said sidewall insulating layers (15.1, 15.2), over said gate oxide layer (10.3), and over said intermediate insulating layer (13, 14), followed by the step of removing selected portions of said continuous electrode layer (16) to expose corresponding portions of said intermediate insulating layer (13, 14).

17. The method of claim 16 in which said electrode layer (16) is essentially polycrystalline silicon.

18. A method of making a MOSFET device comprising the steps of:

(a) forming a pair of spaced-apart field oxide layer portions (11) at a major surface of a semiconductive silicon body (10);

(b) introducing conductivity type determining impurities into the body to form a doped region of predetermined depth (10.5) of the body located contiguous with the major surface thereof in the space between the field oxide layer portions (11), said doped region (10.5) being of opposite type and higher conductivity as compared with the conductivity of the bulk of body (

     10);

(c) depositing a contact electrode layer (12) essentially of metal, metal-silicide, or silicon rich metal-silicide on said field oxide layers (11) and on the exposed portions of said major surface of the body (10) in the space between the field oxide layer portions (11);

(d) forming an intermediate insulating layer (13,

     14) on said contact layer (12);

(e) forming a first aperture penetrating through said insulating layer (13,

     14) and said contact layer (12), thereby separating said contact layer (12) into a pair of spaced-apart contact electrodes (12.1, 12.2); and

thereby exposing a pair of mutually opposed sidewall edges of the contact electrodes (12.1, 12.2) and exposing another portion of the major surface of the body (10) located between said sidewall edges of said contact electrodes (12.1, 12.2);

(f) depositing another insulating layer (15) on said intermediate layer (13,

     14), on said exposed sidewall edges of the contact electrodes (12.1, 12.2), and on said another portion of the major surface of the body (10);

(g) anisotropically etching said another insulating layer (15), whereby material of said another insulating layer (15) remains on said sidewall edges of the contact electrodes (12.1, 12.2), thereby forming mutually opposing sidewall insulating layers (15.1, 15.2) on said sidewall edges and thereby exposing yet another, smaller portion of the major surface of the body (10) therebetween;

(h) thermally growing a gate oxide layer (10.3) on the said yet another, smaller portion of the major surface of the body (10); and

(i) forming a gate electrode layer (16.3) on said gate oxide layer (10.3), on each of said sidewall insulating layers (15.1, 15.2), and on a selected portion of said intermediate insulating layer (13,

     14).

19. The method of claim 18 in which said intermediate insulating layer (13, 14) comprises a silicon nitride layer (14) on a silicon dioxide layer (13).

20. The method of claim 18 or 19 in which, prior to step (h), a recess of predetermined depth greater than that of the doped region (10.5) is formed in the body (10) at said another, smaller portion of the major surface thereof.