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Display device with variable capacity buffer memory

  • US 4,325,063 A
  • Filed: 06/11/1979
  • Issued: 04/13/1982
  • Est. Priority Date: 11/16/1977
  • Status: Expired due to Term
First Claim
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1. A display system comprising:

  • a character code source of coded combinations of bits representing characters;

    a first source of incrementing signals occurring each time a coded combination of bits is emitted by said character code source;

    a display means for visually displaying the characters represented by the coded combinations of bits;

    a second source of incrementing signals occurring each time said display means requires one of said coded combinations of bits;

    a first buffer memory means connecting said character code source to said display means and comprising an addressed memory array having a plurality of addressed storage registers, each of said storage registers being capable of storing one of said coded combinations of bits, and address counter means for generating the addresses of said addressed register, incrementing means for incrementing the count in said address counter means each time an incrementing signal is received from said first or second source, writing means responsive to each incrementing signal from said first source for writing a coded combination of bits from said character code source into an addressed register indicated by said address counter means, and reading means responsive to each incrementing signal from said second source for reading the coded combination bits stored in an addressed register indicated by said address counter means and transferring said coded combination of bits to said display means;

    second buffer memory means connecting said character code source to said display means and comprising an addressed memory array having a plurality of addressed storage registers, each of said storage registers being capable of storing one of said coded combinations of bits, and address counter means for generating the addresses of said addressed registers, incrementing means for incrementing the count in said address counter means each time an incrementing signal is received from said first or second source, writing means responsive to each incrementing signal from said first source for writing a coded combination of bits from said character code source into an addressed register indicated by said address counter means, and reading means responsive to each incrementing signal from said second source for reading the coded combination bits stored in an addressed register indicated by said address counter means and transferring said coded combination of bits to said display means;

    controlled initializing means for cleaning said address counter means each time a set of coded combination of bits is to be transferred to said buffer memory means and each time said set is to be transferred from said buffer memory means to said display means;

    means for controlling said initializing means to clear the address counter means of each of said buffer memory means;

    connecting means for alternately, first, operatively connecting said addressed memory array of said first buffer memory means to said character code source and operatively connecting said addressed memory array of said second buffer memory means to said display means, and, second, operatively connected said addressed memory array of second buffer memory means to said character code source and operatively connecting said addressed memory array of said first memory means to said display means; and

    means for feeding said first incrementing signals to the incrementing means and the writing means of the buffer memory means whose addressed memory array is operatively connected to said character code source and for feeding said second incrementing signals to the incrementing means and the reading means of the buffer memory means whose addressed memory array is operatively connected to said display means.

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