Field effect devices and their fabrication

• US 4,325,073 A
• Filed: 05/31/1979
• Issued: 04/13/1982
• Est. Priority Date: 05/31/1978
• Status: Expired due to Term

• Current Assignee: The secretary of state for defence in her Britannic Majesty's Government of the United Kingdom of Great Britain And Northern Ireland
• Original Assignee: The secretary of state for defence in her Britannic Majesty's Government of the United Kingdom of Great Britain And Northern Ireland
• Inventors: Vokes, John C., Hughes, Brian T., Wight, David R., Redstone, Reuben
• Primary Examiner(s): Ozaki, G.
• Application Number:
  US06/044,274
• Time in Patent Office: 1,048 Days
• Field of Search: 29/571, 29/580, 29/589, 29/590, 148/171, 148/172, 357/23, 357/22
• US Class Current: 257/284
• CPC Class Codes: H01L 21/30612 Etching of AIIIBV compounds
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 23/4825 for devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g. silicon on sapphire devices, i.e. SOS
• CPC Class Codes: H01L 24/26 Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802
• CPC Class Codes: H01L 29/8126 Thin film MESFET's
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01011 Sodium [Na]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

A method of fabricating a field effect transistor comprising the steps of forming an active layer of semiconductor material (GaAs) over a surface of a first substrate of semiconductor material (GaAs), applying a second substrate of insulating material, e.g. glass, over the surface of the active layer, removing the first substrate so that the active layer is now supported on the insulating second substrate, and forming source, drain and gate electrodes over the free surface of the active layer. To facilitate removal of the GaAs first substrate by selective etching, a buffer layer of GaAlAs resistant to the GaAs etchant, may be formed between the active layer and the first substrate, which buffer layer is removed, following removal of first substrate, using a selective etchant to which the GaAs active layer is resistant. The technique is particularly applicable to high frequency FETs requiring a very thin active channel region interfaced to a substrate having good insulating properties.

Claims

1. A method of fabricating a field effect transistor comprising the steps of forming a high quality buffer layer of semiconductor material on the surface of a first substrate of semiconductor material, thereafter forming an active layer of semiconductor material over said buffer layer and over said surface of said first substrate, applying a second substrate of insulating material to the surface of the structure comprising the first substrate, buffer layer, and active layer so that the active layer lies between the two substrates, removing the first substrate and buffer layer, and forming source, drain and gate electrodes over the surface of the active layer opposite the second substrate.

2. A field effect transistor fabricated by the method of claim 1.

3. A method as claimed in claim 1, wherein the buffer layer is removed by etching using a selective etchant which attacks the buffer layer at a faster rate than it attacks the active layer.

4. A method as claimed in claim 3, wherein the first substrate is removed by etching using a selective etchant which attacks the first substrate at a faster rate than it attacks the buffer layer.

5. A method as claimed in claim 1, wherein the first substrate is GaAs, the buffer layer is GaAlAs and the active layer is n-type GaAs.

6. A method as claimed in claim 5, wherein the buffer layer is removed by etching with HF.

7. A method as claimed in claim 1, wherein, following removal of the first substrate and buffer layer, a surface thickness of the active layer, at least in the region on which the gate electrode is to be formed, is removed prior to formation of the gate electrode.

8. A method as claimed in claim 1, wherein prior to applying the second substrate to the structure comprising the first substrate, buffer layer, and active layer, a recess is formed in the active layer, and following removal of the first substrate and buffer layer, the gate electrode is formed on the surface of the active layer immediately opposite the recess.

9. A method as claimed in claim 1, wherein prior to applying the second substrate to the structure comprising the first substrate, buffer layer, and active layer, a non-conducting semiconductor layer is formed over the free surface of the active layer and a region of said non-conducting layer is then removed to define a recess through which a region of the underlying active layer is exposed, and following removal of the first substrate and buffer layer, the gate electrode is formed on the surface of the active layer immediately opposite said recess.

10. A method as claimed in claim 8 or claim 9, wherein, prior to formation of the source, drain and gate electrodes, part of the active layer is removed to define an isolated mesa of said active layer overlying the second substrate, and the source, drain and gate electrodes are then formed over the mesa.

11. A method as claimed in claim 10, wherein each electrode also has a portion which extends continuously over the edge of the mesa to provide a contact pad for external connection to the device.

12. A method as claimed in claim 11, wherein the recess underlying the gate electrode terminates at one end short of the edge of the mesa to provide a surface over which the said portion of the gate electrode extends continuously over the mesa edge.

13. A method as claimed in claim 1 wherein said layers are formed epitaxially.

14. A method as claimed in claim 1, wherein the second substrate is glass applied to the structure comprising the first substrate and the active layer by first applying a coating of SiO₂ to the surface of the said structure, and then fusing the second substrate to the SiO₂ coating.

15. A method as claimed in claim 1, wherein the second substrate is applied to the structure comprising the first substrate, buffer layer, and active layer by means of an insulating adhesive comprising cured polyimide resin.

16. A method as claimed in claim 1, wherein the second substrate is applied to the structure comprising the first substrate, buffer layer, and the active layer by first applying a coating of insulating material and then applying the second substrate to the said coating of insulating material.

17. A method as claimed in claim 16, wherein said coating of insulating material comprises cured polyimide resin, and the second substrate is applied to it by means of an adhesive.

18. A method as claimed in claim 1, wherein said second substrate is formed in situ.

19. A method as claimed in claim 16, wherein said second substrate is formed by moulding.

20. A method as claimed in claim 19, wherein the second substrate comprises polyimide resin cured under pressure before removal of the first substrate.