Apparatus for calculating a check digit for a stream of data read from a document

• US 4,325,117 A
• Filed: 12/31/1979
• Issued: 04/13/1982
• Est. Priority Date: 12/31/1979
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Dawson, Charles W., Parmet, Arthur A.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/108,603
• Time in Patent Office: 834 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 371/25, 371/53, 340/146.3 ED
• US Class Current: 715/210
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/104 using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check

Abstract

Information from a document is read by a reader sorter; the information is organized in fields including a transit field which is made up of 8 decimal digits and a check digit. The 8 decimal digits are each multiplied by a predetermined number which depends on the position of the decimal digit in the transit field as indicated by a position counter. Signals indicative of the decimal digit and the position in the transit field are applied to the address terminals of a Programmable Read Only Memory (PROM). Each address location stores the units position of the product of the multiplication of the decimal digit times the predetermined value. A firmware routine stored in a control memory performs the check digit calculation "on the fly" using the units position of the product from the PROM and certain status bits stored in a scratchpad memory.

Claims

1. A document processing system comprising:

a reader sorter for reading characters sequentially from a document and generating character signals indicative of a starting character of a field, a closing character of said field, and a plurality of numeric characters within said field, said plurality of numeric characters including a check digit character and a plurality of decimal digit characters;

an adapter coupled to said reader sorter and responsive to said character signals representative of said plurality of decimal digit characters for generating a plurality of position count signals indicative of a position of each of said plurality of decimal digit characters in said field, said adapter including a memory unit responsive to said character signals indicative of said plurality of decimal digit signals and a corresponding one of said plurality of position count signals for generating a plurality of product signals, each representative of the units position of the result of the multiplication of said one of said plurality of decimal digit characters by one of a plurality of predetermined numbers as indicated by said corresponding one of said plurality of position count signals; and

,

a microprogrammed controller coupled to said reader sorter and to said adapter and including a control store responsive to said character signals indicative of said starting and said ending characters for generating a first and a second plurality of control signals, said adapter being responsive to said first plurality of control signals for generating said plurality of product signals,

said controller including an arithmetic logic unit responsive to said second plurality of control signals and said plurality of product signals for generating signals indicative of said calculated check digit characters, and being further responsive to said character signals indicative of said check digit character for comparison with said calculated check digit characters.

2. The system of claim 1 wherein said adapter comprises:

a character position counter responsive to a first of said plurality of control signals for resetting said character position counter to a predetermined count when said character signals indicative of said starting character are received by said controller, and responsive to a second of said plurality of control signals for generating count signals indicative of said position of each of said plurality of numeric characters in said field;

said memory means coupled to said character position counter and responsive to said character signals and said count signals for generating said product signals; and

,

a multiplexer coupled to said memory unit and responsive to a third of said plurality of control signals for transferring said product signals and said count signals to said controller.

3. The system of claim 2 wherein said controller comprises:

said microprogrammed control store coupled to said adapter and responsive to said character signals representative of said starting character for generating said first plurality of control signals, including said first control signal for resetting said character position counter, said second control signal for incrementing said character position counter, and said third control signal for enabling said multiplexer for transfer of said product signals and said count signals to said controller.

4. The system of claim 3 wherein said microprogrammed controller further generates a starting field flag in response to receiving said character signals representative of said starting character from said adapter.

5. The system of claim 4 wherein said controller further comprises:

a scratchpad memory for storing bits representative of said check digit character in a first address location, bits representative of a partial sum of said calculated check digit character in a second address location, and a bit representative of said starting flag in a third address location in response to said second plurality of control signals; and

,

said arithmetic logic unit coupled to said scratchpad memory and to said adapter and responsive to scratchpad signals representative of the contents of said second address location and said product signals for generating said partial sum for storage in said second address location when said bit representative of said starting flag is stored in said third address location in response to said second plurality of control signals.

6. The system of claim 5 wherein said controller further generates a closing field flag in response to receiving said character signals representative of said closing character from said adapter.

7. The system of claim 6 wherein said scratchpad memory stores a bit representative of said closing flag in said third address location, said arithmetic logic unit being responsive to said closing flag bit for comparing said first and second address locations for equals indicative of said controller verifying said plurality of numeric characters of said field read by said reader.

8. The system of claim 7 wherein said opening and closing characters and said field is a transit field.