Process and apparatus employing microprogrammed control commands for transferring information between a control processor and communications channels

• US 4,325,119 A
• Filed: 01/19/1977
• Issued: 04/13/1982
• Est. Priority Date: 01/19/1977
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Yu, Kin C., Huettner, Robert E., Grandmaison, John P., Vernon, John H.
• Primary Examiner(s): Thomas, James D.
• Application Number:
  US05/760,783
• Time in Patent Office: 1,910 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/300, 444/1
• US Class Current: 710/5
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 9/226 Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format

Abstract

Firmware generated commands provided by a control store in a microprogrammed communications processor which is coupled in a system including a main memory and a central processing unit control the processing of instructions from the central processing unit, interrupts from the communications channels and servicing of such channels if a channel status change is detected. The firmware also controls the operation of the servicing of such channels by providing a control mechanism by which data is read from or written into the main memory. Further, interrupts which are not handled immediately are handled in a deferred interrupt arrangement.

Claims

1. In a data processing system including a main memory and a plurality of communication channels, said system having a central processing unit and a microprogrammed communication processor including a control element having a program memory storing microprogram instructions to enable said processor to control the transfer of data between said main memory and the other elements of said system, including said central processing unit and said communication channels, a machine implemented process in which said processor is controlled by said stored microprogram instructions to perform the method steps of:

A. determining whether said central processing unit has issued a control instruction to said processor;

B. executing said control instruction if said step of determining indicates that said control instruction has been issued;

C. repeating said steps of determining and executing until said step of determining indicates that said control instruction is not presently issued;

D. determining, if no control instruction is detected during step A, whether one of said channels requires servicing;

E. servicing a said channel requiring servicing if said last-mentioned step of determining indicates such service requirement;

F. repeating said steps of determining, executing, repeating, determining, and servicing until a determination is made that a said channel does not require servicing;

G. accessing control commands associated with a first said communication channel if there is no indication that a channel requires servicing;

H. servicing said first channel if its said control commands indicate that the execution of said control commands is required;

I. repeating said first step of determining and the further steps following said first step of determining until said step of accessing is entered again;

J. repeating said step of accessing for a second said channel;

K. repeating said second mentioned step of servicing for said second said channel; and

L. reentering said first step of determining.

2. A process as in claim 1 further comprising, within step H, the steps of:

A. determining whether said unit may be ready to be interrupted; and

B. interrupting said unit if said processor has indicated a need for interrupt service.

3. A process as in claim 2 further comprising the steps of:

A. generating a channel scan complete signal after each of said channels has been accessed and serviced during said steps G and H; and

B. enabling, in response to said channel scan complete signal, said steps of determining whether said unit may be ready to be interrupted.

4. A process as in claim 3 further comprising the step of enabling said second-mentioned step of servicing before interrupting said unit in response to the indication that said processor needs interrupt service.

5. A process as in claim 1 further comprising the steps of:

A. generating a channel scan complete signal after each of said channels has been accessed and serviced during said step of accessing said second-mentioned step of servicing;

B. determining, in response to said channel scan complete signal, whether said processor has any interrupts pending requiring servicing by said unit;

C. interrupting said unit if said last-mentioned step of determining indicates that a said interrupt is pending;

D. scanning, in response to an indication that no said interrupt is pending, the status of each said channel; and

E. servicing a said channel if its said status indicates that there has been a change in its said status.

6. A process as in claim 5 further comprising, within said step of servicing in response to said status indication, the steps of:

A. determining whether the status of said channel indicates that an interrupt of said unit is required or whether said channel needs servicing by said processor;

B. enabling said processor to service said channel if said last-mentioned step of determining indicates that said channel needs servicing by said processor; and

C. setting a register to indicate that an interrupt to said unit is pending.

7. A process as in claim 6 further comprising the step of reentering the first said step of determining after said step of setting if said step of determining the status of said channel indicates that said channel does not indicate that an interrupt of said unit or servicing by said processor is required.

8. A process as in claim 7 further comprising the steps of:

A. determining, in response to an indication that there is a said interrupt pending, whether said register has been set during said step of setting; and

B. interrupting, in response to said last-mentioned step of determining, said unit if said register has been set.

9. A process as in claim 8 further comprising the steps of:

A. determining whether said unit has indicated that any interrupts which are pending may be currently serviced if requested; and

B. interrupting said unit if said said last-mentioned step of determining indicates that an interrupt is pending and said register has not been set.

10. A process as in claim 9 further comprising the step of reentering the first said step of determining after any of said steps of interrupting said unit or if it is determined that said unit has not indicated that any interrupts which are pending may be currently serviced if requested.

11. A data processing system including a main memory and a plurality of communication channels, said system having a central processing unit and a microprogrammed communication processor including a control element having a program memory storing microprogram instructions and means for applying said microprogram instructions to said processor to enable said processor to control the transfer of data between said main memory and the other elements of said system, including said central processing unit and said communication channels, said processor further comprising the following elements responsive to said microprogram instructions to perform the operations indicated:

A. first means for determining whether said central processing unit has issued a control instruction to said processor;

B. means for executing said control instruction if there is an indication that said control instruction has been issued;

C. means for enabling said means for determining and said means for executing until it is determined that a said control instruction is not presently issued;

D. means for determining whether one of said channels requires servicing;

E. means for servicing a said channel requiring servicing if it is determined that there is such service requirement;

F. means for enabling said means for determining, executing, enabling, determining, and servicing until a determination is made that a said channel does not require servicing;

G. means for accessing control commands associated with a first said communications channel if there is no indication that a channel requires servicing;

H. means for servicing said first channel if its said control commands indicate that the execution of said control commands is required;

I. means for enabling said first means for determining and said means A through F responsive thereto until said means for accessing is again entered;

J. means for enabling the means for accessing for a second said channel;

K. means for enabling means H for servicing for said second said channel; and

L. means for reenabling said first means for determining after the servicing of said second said channel.

12. A processor as in claim 11 further comprising:

A. means responsive to said means H for determining whether said unit may be ready to be interrupted; and

B. means for interrupting said unit if said processor has indicated a need for interrupt service.

13. A processor as in claim 11 further comprising:

A. means for generating a channel scan complete signal after each of said channels has been accessed and serviced;

B. means for determining, in response to said channel scan complete signal, whether said processor has any interrupts pending requiring servicing by said unit;

C. means for interrupting said unit if said last-mentioned means for determining indicates that a said interrupt is pending;

D. means for scanning, in response to an indication that no said interrupt is pending, the status of each said channel; and

E. means for servicing a said channel if its said status indicates that there has been a change in its said status.

14. A processor as in claim 13 further comprising:

A. means for determining whether the status of said channel indicates that an interrupt of said unit is required or whether said channel needs servicing by said processor.

B. means for enabling said processor to service said channel if said last-mentioned means for determining indicates that said channel needs servicing by said processor; and

C. means for setting a register to indicate that an interrupt to said unit is pending.