Reprogrammable control apparatus

• US 4,325,130 A
• Filed: 03/10/1980
• Issued: 04/13/1982
• Est. Priority Date: 03/16/1979
• Status: Expired due to Term

• Current Assignee: Mannesmann AG (Vodafone Group PLC)
• Original Assignee: Mannesmann AG (Vodafone Group PLC)
• Inventors: Tiltscher, Gerald
• Primary Examiner(s): Springborn, Harvey E.
• Application Number:
  US06/128,482
• Time in Patent Office: 764 Days
• Field of Search: 307/458, 307/563, 307/317 A, 364/200 MS File, 364/900 MS File
• US Class Current: 711/103
• CPC Class Codes: G05B 19/045 using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers
• CPC Class Codes: G05B 19/106 for selecting a programme, variable or parameter

Abstract

An electrically programmable and erasable ROM (EPROM) is accessed via a selector and an address counter, all mounted on a PC board which includes also a regular VCC bus. The EPROM output lines feed an output circuit, parts of which may be on other boards. The board, however, has additional terminals connected to the EPROM output lines in addition to a protective circuit limiting the voltage level in the output circuit in case high reprogramming signals are applied by an external unit to some of these additional terminals for programming via the EPROM output terminal. One of the latter terminals connects to the VCC input of the EPROM and a Schottky diode connects the VCC bus to that input to protect the latter bus from a higher-than-normal supply voltage needed during reprogramming.

Claims

1. In a control apparatus which includes an electrically programmable ROM, addressing means connected to addressing inputs of the ROM, and an output circuitry connected to output terminals of the ROM, the output circuitry, the addressing means, and the ROM operating at a particular voltage level for addressing and ROM content readout operation, there being a voltage supply bus for connection to a source of regular voltage supply and connected for feeding power to the output circuit and the addressing means, the combination comprising:

a plurality of particular terminals not being used for regular readout and being electrically connected to the ROM in addition to said output circuitry;

a protective circuit for protection of the ROM and being connected to the said output circuit to limit the voltage level thereof for voltages applied via some of said particular terminals to the output terminals of the ROM;

one of the particular terminals provided for receiving a relatively high supply voltage, higher than the particular voltage level for purposes of reprogramming the ROM; and

a Schottky diode connected to said one particular terminal to a voltage supply terminal of said ROM, and to said voltage supply bus for feeding the regular supply voltage as applied to the ROM via the diode and, thereby, to bias the diode in forward direction, the high supply voltage, upon being applied being appied to said one particular terminal, biasing the diode in the reverse.

2. In a control apparatus as in claim 1, said protective circuit including, for each output terminal, a series circuit of a Zener diode and a resistor having a common junction, there being as many series circuits and junctions as there are ROM output terminals, the junctions being connected to the output circuit, the resistors being respectively connected to the ROM output terminals, the Zener diodes being biased additionally, for limiting voltages at the junctions to a level below said relatively high supply voltage.

3. In a control apparatus as set forth in claim 1 or 2, wherein the addressing means includes a selector connected to a high-order address portion of the ROM, and a counter connected to a low-order address portion of the ROM, the counter having a reset input connected to one of the output terminals of the ROM and constituting part of the output circuit in that regard.

4. The combination as in claim 1 or 2, in combination with a printer which issues line advance pulses and wherein the addressing means includes a selector connected to a high-order address portion of the ROM and a counter connected to a low-order address portion of the ROM, the counter being connected for counting line advance pulses from the printer.