Electronic speed control system for automotive vehicles

• US 4,325,336 A
• Filed: 07/18/1980
• Issued: 04/20/1982
• Est. Priority Date: 07/20/1979
• Status: Expired due to Term

• Current Assignee: Nippon Soken, Inc. (DENSO Corporation)
• Original Assignee: Nippon Soken, Inc. (DENSO Corporation)
• Inventors: Matsui, Takeshi, Shinoda, Yoshio, Kuno, Akira
• Primary Examiner(s): Lall, P. S.
• Application Number:
  US06/170,088
• Time in Patent Office: 641 Days
• Field of Search: 123/350, 123/352, 123/354, 123/355, 364/431, 180/176, 180/179
• US Class Current: 123/350
• CPC Class Codes: B60K 31/042 where at least one electrical quantity is set by the vehicle operator
• CPC Class Codes: B60K 31/107 the memory being digital
• CPC Class Codes: B60W 2520/105 Longitudinal acceleration
• CPC Class Codes: F02D 31/002 controlling air supply
• CPC Class Codes: F02D 31/006 for maximum speed control
• CPC Class Codes: F02D 41/2403 using essentially up/down counters

Abstract

In a speed control system for vehicles, a speed-difference calculation circuit calculates an absolute value of a time difference between a predetermined period of time corresponding with a desired speed and the actual period of time corresponding with the actual speed, an acceleration calculation circuit calculates an absolute value of a time difference between the preceding and following actual periods of time within a limited range, and correction signal generator calculates a sum of the absolute values when each sign of the calculated time differences is positive or negative and calculates a difference between the absolute values when respective signs of the calculated time differences are opposite to each other. The signal generator selectively produces correction signals related to the calculated sum and the calculated difference. A distribution circuit produces a control signal in response to the respective correction signals, and an actuator controls the opening angle of the engine throttle in response to the control signal.

Claims

1. A speed control system for an automotive vehicle driven by an internal combustion engine under control of a throttle valve, the control system comprising:

first means for producing a timing signal with a period of time responsive to the actual speed of the vehicle;

second means for producing a command signal indicative of a predetermined period of time defined by a desired speed of the vehicle;

third means responsive to the timing signal for calculating a first time difference between the predetermined period of time and the actual period of time of the timing signal and for producing a first difference signal indicative of an absolute value of the calculated first time difference and a first sign signal indicative of the positive or negative sign of the calculated first time difference;

fourth means responsive to the timing signal for calculating a second time difference between respective actual periods of time of the preceding and following timing signals and for producing a second difference signal indicative of an absolute value of the calculated second time differene and a second sign signal indicative of the positive or negative sign of the calculated second time difference;

fifth means for limiting a value of the second difference signal to a predetermined maximum value when the actual acceleration of the vehicle exceeds a maximum value;

sixth means responsive to the timing signal for calculating a sum of the absolute values when respective signs of the first and second sign signals are identical to each other and for calculating a difference between the absolute values when respective signs of the first and second sign signals are opposite to each other, said sixth means selectively producing first and second correction signals respectively indicative of the calculated sum and the calculated difference and ceasing to produce the first and second correction signals when the respective calculated values are zero;

seventh means responsive to the timing signal and one of the first and second correction signals for selectively producing first and second control signals respectively in relation to the positive and negative signs of the second sign signal; and

actuator means for decreasing and increasing the opening angle of said throttle valve respectively in response to the first and second control signals.

2. A speed control system as claimed in claim 1, wherein said fifth means is arranged to limit a value of the second difference signal to a predetermined maximum value when the actual acceleration of the vehicle exceeds a maximum value relative to each command speed of the vehicle.

3. A speed control system as claimed in claim 1, wherein said fifth means is arranged to limit a value of the second difference signal to a predetermined maximum value when the actual acceleration of the vehicle exceeds 0.02 gravity.

4. A speed control system as claimed in claim 1, further comprising a clock circuit for producing a series of clock signals at a constant frequency in sequence;

and wherein said fourth means includes a first counter circuit for counting the number of the clock signals defined by the proceding timing signal, and a second counter circuit for counting down the number of the previously counted clock signals responsive to the following timing signal when a period of time of the preceding timing signal is longer than that of the following timing signal and successively counting up the number of the clock signals defined by the following timing signal after completion of counting down the number of the previously counted clock signals when a period of time of the preceding timing signal is shorter than that of the following timing signal, said second counter circuit producing a second difference signal indicative of an absolute value of a difference between the number of the clock signals respectively defined by the preceding and following timing signals and producing second positive and negative sign signals respectively when the number of the previously counted clock signals is counted down and when the number of the clock signals defined by the following timing signal is counted up, and wherein said fifth means is a logic circuit for limiting a value of the second difference signal to a predetermined maximum value when the actual acceleration of the vehicle exceeds a maximum value relative to each command speed of the vehicle.

5. A speed control system as claimed in claim 4, wherein said logic circuit comprises a plurality of OR-gates for applying the second difference signal therethrough to said sixth means when a value of the second difference signal is less than a predetermined maximum value and another OR-gate for applying a second difference signal indicative of the said predetermined maximum value through said first-named OR-gates when a value of the second difference signal exceeds the said predetermined maximum value.