Architecture for data processor

• US 4,326,247 A
• Filed: 09/25/1978
• Issued: 04/20/1982
• Est. Priority Date: 09/25/1978
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Chamberlin, George P.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Eng, David Y.
• Application Number:
  US05/946,222
• Time in Patent Office: 1,303 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/42
• CPC Class Codes: G06F 9/4825 Interrupt from clock, e.g. time of day

Abstract

A data processor having an internal address bus and a separate internal data bus which are selectively coupled to an external memory bus. The external memory bus is time shared so that it can carry memory addresses as well as data. A command shift register, at least one capture register, a timer register, a compare register, a control register, and a status register are all coupled to the internal data bus. The command shift register is capable of serially shifting data, upon command, to an output terminal. The at least one capture register is capable of being loaded from the timer register whenever a transition occurs on a predetermined input to the data processor thereby capturing the time at which the transition occurred. The compare register is used to store a digital signal equivalent to some desired time. The compare register is continuously compared for equality with the timer register and provides a signal when equality exists. The control register is capable of providing software control of preselected registers within the data processor and the status register is used to temporarily store data indicating causes of interrupts.

Claims

1. A data processing system having an N-bit data bus, an M-bit data bus, and an M+N bit data address bus, and comprising:

an instruction decoder for decoding instructions for the data processing system;

an instruction register coupled to the instruction decoder for holding instructions to be decoded by the instruction decoder;

an array of registers for storing variable data, the array of registers being coupled to the N-bit data bus;

an arithmetic and logic unit coupled to the N-bit data bus and coupled to the instruction decoder, the arithmetic and logic unit being capable of performing operations on the data stored in the array of registers;

a program counter for controlling sequence of instructions, the program counter being coupled to the address bus;

a timer register capable of being incremented by one at a continuous rate, the timer register being coupled to the N-bit data bus;

at least one capture register being capable of being loaded from the timer register, the at least one capture register being coupled to the N-bit data bus, to the timer register, and to an input terminal of the data processor system to allow the at least one capture register to be loaded from the timer register whenever a signal transition occurs on the input terminal;

a compare register coupled to the N-bit data bus, the compare register being capable of being continuously compared for equality with the timer register to provide a signal when equality exists, the timer register thereby being capable of providing an output to the at least one capture register and of providing an output to be compared; and

a command shift register coupled to the N-bit data bus and to an output terminal of the data processing system, the command shift register providing temporary storage of data and shifting the data out to the output terminal upon a predetermined command.

2. A data processing system as recited in claim 1 further including a control register coupled to the N-bit data bus, the control register providing software control of at least the command shift register;

and a status register coupled to the N-bit data bus for temporarily storing data indicating causes of interrupts.

3. A data processing system as recited in claim 1 wherein the N-bit data bus is an eight-bit bus, the M-bit data bus is a three-bit bus and has a first portion and a second portion, and the M+N bit address bus is an eleven-bit bus and has a first portion and a second portion.

4. A data processing system as recited in claim 3 further including an interface bus for interfacing the data processing system with external circuitry, and means for selectively coupling the first portion of the address bus to the interface bus or coupling the N-bit and the first portion of the M-bit data buses to the interface bus.