Power source device for bubble memory unit

• US 4,327,422 A
• Filed: 07/17/1980
• Issued: 04/27/1982
• Est. Priority Date: 07/19/1979
• Status: Expired due to Term

• Current Assignee: Fujitsu Fanuc Ltd (Fanuc Corporation)
• Original Assignee: Fujitsu Fanuc Ltd (Fanuc Corporation)
• Inventors: Hattori, Masayuki, Imazeki, Ryoji
• Primary Examiner(s): Moffitt, James W.
• Application Number:
  US06/169,791
• Time in Patent Office: 649 Days
• Field of Search: 365/1, 365/226, 365/227, 365/228, 365/229, 365/194
• US Class Current: 365/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G11C 19/085 Generating magnetic fields therefor, e.g. uniform magnetic field for magnetic domain stabilisation
• CPC Class Codes: H02H 3/247 having timing means

Abstract

A power source device for a bubble memory unit, wherein there is supplied a first DC voltage E_c which is applied to control circuitry for controlling the reading and writing of data, a second DC voltage signal E_d which is applied to drive circuitry for driving a bubble memory element, and a memory signal M_e which enables data to be written in or read from the bubble memory element, the signals E_c, E_d and M_e being made to rise and fall according to a prescribed sequence as a commercial power supply is connected and disconnected. The power source device includes first and second DC power source circuits, a comparator circuit for comparing the magnitude of the first DC voltage E_c with a reference level V_M having a value greater than an allowable lower limit value, and a delay circuit. The second DC power source circuit is actuated following a prescribed time delay which begins when the value of signal E_c surpasses the reference level V_M at the time that the commercial power supply is connected, and the memory enable signal M_e is produced after the second DC power source circuit has been actuated. The memory enable signal M_e is made to vanish when the magnitude of signal E_c drops below the reference potential V_m at the time that the commercial power supply is disconnected, the second DC power source circuit being rendered non-operational following a prescribed time delay.

Claims

1. A power source device for a bubble memory unit having a control circuit, a drive circuit, and a bubble memory element, said power source device for supplying a first DC voltage signal E_c which is applied to the control circuit for controlling the reading and writing of data, a second DC voltage signal E_d which is applied to the drive circuit for driving the bubble memory element, and a memory enable signal M_e which enables data to be written in the bubble memory element or read out therefrom, the signals E_c, E_d and M_e being made to rise and fall according to a prescribed sequence as a commercial power supply is connected and disconnected, said power source device comprising:

a first DC power source circuit, coupled to the commercial power supply, for generating a reference level voltage V_M and said first DC voltage signal E_c ;

a second DC power source circuit, coupled to the commercial power supply, for generating said second DC voltage signal E_d ;

a comparator circuit for comparing the magnitude of said first DC voltage signal E_c with said reference level voltage V_M and for generating a comparison signal;

signal generating means, coupled to said comparator circuit, for generating the memory enable signal M_e ; and

delay means for delaying said comparison signal and for providing a power enable signal P_e, corresponding to the delayed comparison signal, to said second DC power source circuit;

wherein when the commercial power supply has been connected, and after the lapse of time until the comparison signal indicates that the magnitude of said first DC voltage signal E_c surpasses the reference level voltage V_M, said delay means generating said power enable signal P_e, said power enable signal P_e actuating said second DC power source circuit so that said second DC voltage signal E_d is generated and thereafter said signal generating means generates the memory enable signal M_e.

2. The power source device as set forth in claim 1, further comprising a rapid discharge circuit connected across the output terminals of said second DC power source circuit and connected to said delay means, said rapid discharge circuit operational until the power enable signal P_e is generated by said delay means, said rapid discharge circuit rendered non-operational by the generation of the power enable signal P_e.

3. The power source device as set forth in claim 1 or 2, wherein the reference level voltage V_M is less than a set value V_N of the first DC voltage E_c and greater than an allowable lower limit voltage V_L.

4. The power source device as set forth in claim 1 or 2, wherein the commercial power supply generates an AC input voltage and wherein said second DC power source circuit comprises:

means for generating a reference voltage;

a first rectifier circuit for rectifying the AC input voltage;

a power transistor, connected to said first rectifier circuit, for generating a voltage signal having a rectangular waveform;

a pulse width modulator, operatively connected to the base of said power transistor, for generating a modulating signal to turn the power transistor on and off;

a second rectifier circuit, operatively connected to said power transistor, for rectifying the voltage signal which has been pulse-width modulated by said pulse width modulator and for providing, as an output, said second DC voltage signal E_d ;

a comparator circuit, operatively connected to said second rectifier circuit, for comparing the magnitudes of said second DC voltage signal E_d and the reference voltage and for actuating said pulse width modulator in dependence upon the result of the comparison; and

a gate circuit, connected between said power transistor and said pulse width modulator and connected to said delay means, for gating the output of said pulse width modulator so as to turn said power transistor on and off;

said gate circuit responding to the generation of the power enable signal P_e to pass the output of the pulse width modulator, whereby said power transistor is turned on or off in accordance with the output of the pulse width modulator to control the output of the DC voltage signal E_d from said second rectifier.

5. A power source device for a bubble memory unit having a control circuit for controlling the reading and writing of data, a bubble element, and a drive circuit for driving the bubble element, said power source device for supplying a first DC voltage signal E_c to the control circuit, a second DC voltage signal E_d to the drive circuit for driving the bubble memory element, and a memory enable signal M_e for enabling data to be written in or read out of the bubble memory element, said signals E_c, E_d and M_e being made to rise and fall according to a prescribed sequence as a commercial power supply is connected and disconnected, said power source device comprising:

a first DC power source circuit, coupled to the commercial power supply, for generating a reference voltage V_M and said first DC voltage signal E_c ;

a second DC power source circuit, coupled to the commercial power supply, for generating said second DC voltage signal E_d ;

a comparator circuit for comparing the magnitude of said first DC voltage signal E_c with said reference level voltage V_M and for generating a comparison signal; and

delay means for delaying said comparison signal and for providing a power enable signal P_e, corresponding to the delayed comparison signal, to said second DC power source circuit;

the memory enable signal M_e ceasing immediately when the value of the first DC voltage signal E_c drops below the reference voltage Vm at the time that the commercial power supply is disconnected;

said second DC power source circuit rendered non-operative a prescribed period of time, determined by said delay means, after the memory enable signal M_e ceases.

6. The power source device as set forth in claim 5, further comprising a rapid discharge circuit connected across the output terminals of said second DC power source circuit and operatively connected to said delay means, said rapid discharge circuit rendered operational after said prescribed period of time.

7. The power source device as set forth in claim 5 or 6, wherein the commercial power supply generates an AC input voltage and wherein said second DC power source circuit comprises:

means for generating a reference voltage;

a first rectifier circuit for rectifying the AC input voltage;

a power transistor, connected to said first rectifier circuit, for generating a voltage signal having a rectangular waveform;

a pulse width modulator circuit, operatively connected to the base of said power transistor, for modulating said voltage signal by turning the power transistor on and off;

a second rectifier circuit, operatively connected to said power transistor, for rectifying the voltage signal which has been pulse-width modulated by said pulse width modulator and for providing, as an output, said second DC voltage signal E_d ;

a comparator circuit, operatively connected to said second rectifier circuit and to the means for generating a reference voltage, for comparing the magnitudes of the second DC voltage signal E_d and the reference voltage and for actuating said pulse width modulator in dependence upon the result of the comparison; and

a gate circuit, connected between said power transistor and said pulse width modulator and connected to said delay means, for gating the output of said pulse width modulator so as to turn said power transistor on and off;

said gate circuit closed after said prescribed period of time to block the output of said pulse width modulator, whereby said power transistor is turned off.

8. The power source device as set forth in claim 5 or 6, wherein the reference level voltage V_M is less than a set value V_N of the first DC voltage E_c and greater than an allowable lower limit voltage V_L.

9. A power source device for a bubble memory unit having a bubble memory element, a control circuit for controlling the reading and writing of information with respect to the bubble memory element and a drive circuit for driving the bubble memory element, said power source device connected to a commercial power supply, said power source device comprising:

a first DC power source circuit, coupled to the commercial power supply, for generating a first reference voltage signal and a first DC voltage signal, said first DC voltage signal provided to the control circuit of the bubble memory unit;

a second DC power source circuit, coupled to the commercial power supply, for generating a second DC voltage signal provided to the drive circuit of the bubble memory unit;

comparator means, operatively connected to said first DC power source circuit, for comparing said first reference voltage signal and said first DC voltage signal, and for providing, as an output, a comparison signal;

signal generating means, operatively connected to said comparator means, for receiving said comparison signal and for providing a memory enable signal to the control circuit in dependence upon said comparison signal;

delay means, operatively connected between said comparator means and said second DC power source circuit, for delaying said comparison signal and for generating a power enable signal corresponding to the delayed comparison signal;

wherein, at a time after the commercial power supply is connected said comparison signal indicates that said first DC voltage signal is greater than said first reference voltage signal whereupon said delay means will generate said power enable signal which will actuate said second DC power source circuit so that said second DC voltage signal is generated, said signal generating means generating said memory enable signal after said second DC voltage signal has been generated.

10. A power source device as set forth in claim 9, further comprising a rapid discharge circuit, connected across the output terminals of said second DC power source circuit and operatively connected to said delay means, for short circuiting the output of said DC power source circuit until said power enable signal indicates that said first DC voltage signal is greater than said first reference voltage signal at which time said rapid discharge circuit is rendered non-operational.

11. A power source device as set forth in claim 10, wherein said rapid discharge circuit comprises a thyristor having first and second terminals connected to the output terminals of said second DC power source circuit and having a gate operatively connected to the output of said delay means.

12. A power source device as set forth in claim 9 or 10, wherein said first DC voltage signal has a maximum set value which is greater than said first reference voltage signal and wherein said first DC voltage signal has a lower limit value which is less than said first DC voltage signal.

13. A power source device as set forth in claim 9 or 10, wherein the commercial power supply generates an AC input voltage and wherein said second DC power source circuit comprises:

a first rectifier circuit for rectifying the AC input voltage;

means for providing a second reference voltage;

first differential amplifier means for comparing said second reference voltage signal to said second DC voltage signal and for generating a first difference signal;

first pulse width modulator means for providing, as an output, a first modulation signal in dependence upon said first difference signal;

an AND gate having a first input connected to the output of said first pulse width modulator means and having a second input connected to the output of said delay means, said AND gate for providing, as an output, said first modulation signal in dependence upon said power enable signal; and

power control circuit means, operatively connected to said first rectifier circuit, said differential amplifier means and said AND gate, for generating said second DC voltage signal in dependence upon said first modulation signal provided at the output of said AND gate.

14. A power source device as set forth in claim 13, wherein said power control circuit means comprises:

a first power transistor, having a base connected to the output of said AND gate, having an emitter connected to said first rectifier circuit and having a collector;

a first transformer, connected to said first rectifier circuit and to the collector of said first power transistor; and

a second rectifier circuit connected to said first transformer, said second rectifier circuit providing, as an output, said second DC voltage signal, whereby said first power transistor is turned on or off in accordance with the output of said AND gate to control said second DC voltage signal.

15. A power source device as set forth in claim 14, wherein said first DC power source circuit comprises:

a third rectifier circuit for rectifying the AC input voltage;

means for generating a third reference voltage signal;

second differential amplifier means for comparing said first DC voltage signal and said third reference voltage signal and for generating a second difference signal;

second pulse width modulator means for generating a second modulation signal in dependence upon said second difference signal;

a second power transistor, having a base connected to the output of said second pulse width modulator means, having an emitter connected to said third rectifier circuit and having a collector;

a second transformer connected to the collector of said second power transistor and to said third rectifier circuit; and

a fourth rectifier circuit connected to said second transformer, for generating said first DC voltage signal, whereby said second power transistor is turned on or off in accordance with the output of said second pulse width modulator means to control said first DC voltage signal.

16. A power source device as set forth in claim 15, wherein said signal generating means comprises:

second delay means connected to the output of said comparator means, for generating a delayed enable comparison signal; and

a second AND gate, having a first input connected to the output of said second delay means and having a second input connected to the output of said comparator means, for generating said memory enable signal when both said comparison signal and said delayed enable comparison signal are present.

17. A power source device for a bubble memory unit, said power source device connected to a commercial power supply, said power source device comprising:

a first DC power source circuit, coupled to the commercial power supply, for generating a first reference voltage signal and a first DC voltage signal, said first DC voltage signal provided to the bubble memory unit;

a second DC power source circuit, coupled to the commercial power supply, for generating a second DC voltage signal provided to the bubble memory unit;

comparator means, operatively connected to said first DC power source circuit, for comparing said first reference voltage signal and said first DC voltage signal, and for providing, as an output, a comparison signal;

signal generating means, operatively connected to said comparator means, for receiving said comparison signal and for providing a memory enable signal to the bubble memory unit in dependence upon said comparison signal;

delay means, operatively connected between said comparator means and said second DC power source circuit, for delaying said comparison signal and for generating a power enable signal corresponding to said delayed comparison signal;

wherein, at a time after the commercial power supply is connected, said comparison signal indicates that said first DC first voltage signal is greater than said first reference voltage signal whereupon said delay means will generate said power enable signal which will actuate said second DC power source circuit so that said second DC voltage signal is generated, said signal generating means generating said memory enable signal after said second DC voltage signal has been generated.