Digital receiver/transceiver synchronization pulse detector for a multiplexing system

• US 4,328,578 A
• Filed: 12/31/1979
• Issued: 05/04/1982
• Est. Priority Date: 12/31/1979
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Christians, Scott T., Bell, Robert R.
• Primary Examiner(s): STEWART, DAVID
• Application Number:
  US06/108,425
• Time in Patent Office: 855 Days
• Field of Search: 455/73, 455/76, 455/77, 455/78, 455/88, 455/151-152, 455/154, 455/158, 455/160, 455/165, 455/166, 455/183, 455/185, 455/186, 455/352-355, 455/142, 455/145 , 455/146-147, 370/9, 370/100, 375/106
• US Class Current: 370/518
• CPC Class Codes: H03J 1/005 in a loop
• CPC Class Codes: H03J 9/00 Remote-control of tuned circuits; Combined remote-control of tuning and other functions, e.g. brightness, amplification mechanical remote-control arrangements H03J1/00 ; using a microprocessor H03J1/0025; constructional details of remote control switching devices H01H9/0235
• CPC Class Codes: H04B 1/401 for selecting or indicating operating mode

Abstract

A radio transceiver is disclosed having manual controls on a microphone and the remainder of the circuitry located in a main chassis. The microphone and chassis are connected by means of a multiconductor cable, and time sharing multiplexing techniques are utilized and serially transmit information, bidirectionally, along a common data line while a clock line is utilized to synchronize the operation of main chassis and microphone circuitry. Multiple bit binary coded digital words are sent to the microphone to activate microphone displays while analog signals are sent from the microphone to the main chassis to provide analog control signals for the transceiver.

A digital synchronizing pulse detector is disclosed for use in the above transceiver multiplexing system. The detector identifies synchronizing pulses which occur in the clock signal wherein the identification insures the synchronization of microphone and main chassis circuitry.

The transceiver provides for designating a subset of all of the available communication channels as desired channels, and in a memory mode the transceiver is tuned only to those desired channels. Distinctive visual displays are produced indicating if any channels have been designated as desired channels, and if all possible storage space for storing desired channel identification has been utilized. In addition, the dual use of a few pushbuttons is disclosed such that the sequence in which these pushbuttons are actuated determines the transceiver mode of operation selected.

Claims

1. A receiver including a synchronization system in which the operation of local and remote switching circuits are synchronized by a received clock signal, said receiver and synchronization system including:

receiver means located in a main receiver chassis for receiving information transmitted on at least a predetermined channel and providing corresponding indicative signals in response thereto;

local and remote receiver switching circuits, said local switching circuit located in said main receiver chassis and said remote switching circuit located on a receiver remote control unit effectively electrically coupled to said main chassis, each of said switching circuits commencing a predetermined sequence of switching operations in accordance with the occurrence of received short duration clock pulses contained in a received clock signal once a periodic relatively long duration synchronization pulse, having a first duration, in the clock signal is detected as occurring, said short duration pulses having lesser durations than said first duration;

at least one of said local and remote switching circuits including a digital synchronization pulse detector for detecting said periodic synchronization pulses contained in said clock signal, said digital synchronization pulse detector comprising;

terminal means for receiving said clock signal which has said periodic synchronization pulses of said first duration and said short duration pulses;

oscillator means for producing a fixed frequency signal having a predetermined periodic repetition rate insuring the occurrence of a substantial number of cycles of said fixed frequency signal during said first duration of the synchronization pulses of the clock signal;

counter means for receiving, during said clock signal pulses, said fixed frequency signal and developing a count related to the number of cycles of said fixed frequency signal received, said counter means having a maximum capacity of N counts and including an overflow terminal means at which an indicative signal is produced when the N count capacity of said counter means is exceeded, said counter means also having a reset terminal means for reinitializing the count of said counter means in response to received pulses, said terminal means coupled to said reset terminal means wherein for said synchronization pulses of said first duration the count in said counter means will exceed N counts resulting in indicating the detection of a synchronization pulse by providing an indicative signal at said overflow terminal means, and wherein said lesser duration pulses result in resetting the count of said counter means before said counter means can attain a count of N counts, said indicative signal at said overflow terminal means coupled to one of said local and remote switching circuits to insure proper synchronous operation of said local and remote switching circuits.

2. A receiver including a synchronization system in which the operation of local and remote switching circuits are synchronized by a received clock signal, said receiver and synchronization system including;

receiver means located in a main receiver chassis for receiving information transmitted on at least a predetermined channel and providing corresponding indicative signals in response thereto;

local and remote receiver switching circuits, said local switching circuit located in said main receiver chassis on said remote switching circuit located on a receiver remote control unit coupled to said main chassis by a multiwire cable, each of said switching circuits commencing a predetermined sequence of switching operations in accordance with the occurrence of received short duration clock pulses contained in a received clock signal once a periodic relatively long duration synchronization pulse, having a first duration, in the clock signal is detected as occurring, said short duration pulses having lesser durations than said first duration;

at least one of said local and remote switching circuits including a digital synchronization pulse detector for detecting said periodic synchronization pulses contained in said clock signal, said digital synchronization pulse detector comprising;

terminal means for receiving said clock signal which has said periodic synchronization pulses of said first duration and said short duration pulses;

oscillator means for producing a fixed frequency signal having a predetermined periodic repetition rate insuring the occurrence of a substantial number of cycles of said fixed frequency signal during said first duration of the synchronization pulses of the clock signal;

counter means for receiving, during said clock signal pulses, said fixed frequency signal and developing a count related to the number of cycles of said fixed frequency signal received, said counter means having a maximum capacity of N counts and including an overflow terminal means at which an indicative signal is produced when the N count capacity of said counter means is exceeded, said counter means also having a reset terminal means for reinitializing the count of said counter means in response to received pulses, said terminal means coupled to said reset terminal means wherein for said synchronization pulses of said first duration the count in said counter means will exceed N counts resulting in indicating the detecting of a synchronization pulse by providing an indicative signal at said overflow terminal means, and wherein said lesser duration pulses result in resetting the count of said counter means before said counter means can attain a count of N counts, said indicative signal at said overflow terminal means coupled to one of said local and remote switching circuits to insure proper synchronous operation of said local and remote switching circuits.

3. A receiver including a time shared multiplexing system in which local and remote receiver circuits receive/transmit series data signals over a single common data line, the operation of said local and remote circuits each being synchronized by a received clock signal, said receiver and multiplex system comprising;

receiver means located in a main receiver chassis for receiving information transmitted on at least a predetermined channel and providing corresponding indicative signals in response thereto;

local and remote receiver switching circuits, said local switching circuit located in said main receiver chassis and said remote switching circuit located on a receiver remote control unit coupled to said main chassis by a multiwire cable, each of said switching circuits commencing a predetermined sequence of switching operations resulting in the sequential transmission of data between said receiver chassis and said remote control unit over a data conductor in said cable in accordance with the occurrence of received short duration clock pulses contained in a received clock signal once a periodic relatively long duration synchronization pulse, having a first duration, in the clock signal is detected as occurring, said short duration pulses having lesser durations than said first duration;

at least one of said local and remote switching circuits including a digital synchronization pulse detector for detecting said periodic synchronization pulses contained in said clock signal, said digital synchronization pulse detector comprising;

terminal means for receiving said clock signal which has said periodic synchronization pulses of said first duration and said short duration pulses;

oscillator means for producing a fixed frequency signal having a predetermined periodic repetition rate insuring the occurrence of a substantial number of cycles of said fixed frequency signal during said first duration of the synchronization pulses of said clock signal;

counter means for receiving, during said clock signal pulses, said fixed frequency signal and developing a count related to the number of cycles of said fixed frequency signal received, said counter means having a maximum capacity of N counts and including an overflow terminal means at which an indicative signal is produced when the N count capacity of said counter means is exceeded, said counter means also having a reset terminal means for reinitializing the count of said counter means in response to received pulses, said terminal means coupled to said reset terminal means wherein for said synchronization pulses of said first duration the count in said counter means will exceed N counts resulting in indicating the detection of a synchronization pulse by providing an indicative signal at said overflow terminal means, and wherein said lesser duration pulses result in resetting the count of said counter means before said counter means can attain a count of N counts, said indicative signal at said overflow terminal means coupled to one of said local and remote switching circuits to insure proper synchronous operation of said local and remote switching circuits.

4. A receiver time shared multiplex system according to claim 3 wherein said remote control unit comprises a microphone.

5. A receiver time shared multiplex system according to claims 3 or 4 wherein said clock signal is coupled between said main receiver chassis and said remote control unit by a conductor in said cable other than said data conductor.