Phase slip detector and systems employing the detector

• US 4,328,587 A
• Filed: 01/25/1980
• Issued: 05/04/1982
• Est. Priority Date: 02/19/1979
• Status: Expired due to Term

• Current Assignee: Kokusai Densin Denwa Kabushiki Kaisha
• Original Assignee: Kokusai Densin Denwa Kabushiki Kaisha
• Inventors: Mizuno, Toshio, Muratani, Takuro
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US06/115,534
• Time in Patent Office: 830 Days
• Field of Search: 329/2, 329/103, 329/110, 329/118, 329/112, 329/137, 375/8, 375/9, 375/79, 375/80, 375/94, 375/99, 375/111, 375/118, 375/119, 375/97, 375/83, 455/205, 455/206, 455/296, 455/305, 455/312, 455/337
• US Class Current: 375/344
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop
• CPC Class Codes: H04L 27/2275 wherein the carrier recovery circuit uses the received modulated signals

Abstract

A phase slip detector and systems employing said detector comprises a frequency detector for detecting an instantaneous value of received carrier frequency and an integrator for integrating the output of said detector, and determines an occurrence of phase slip by detecting the output level of the integrator larger than predetermind threshold level. Application of the phase slip detector to a carrier recovery system makes it possible to obtain a correct recovered carrier without the effect of phase slip, and application of the detector to a demodulated data compensation system makes it possible to obtain received or demodulated data compressed in generation of burst error and free from the effect of the phase slip.

Claims

1. A carrier recovery circuit comprising:

a carrier regeneration circuit for extracting the regenerated carrier component from a digital PSK wave,

a frequency detector for detecting the instantaneous value of the output frequency of said carrier regeneration circuit,

an integrator for integrating the output signal of said frequency detector,

a threshold circuit coupled to said integrator,

a phase shifter having an input coupled via delay means to the output of said carrier regeneration circuit whereby said phase shifter receives a delayed output of said carrier regeneration circuit, and

means for coupling the output of said threshold circuit to a control terminal of said phase shifter, said phase shifter being operative to shift by a predetermined discrete amount the phase of the input regenerated carrier component in response to the polarity of the integrator output which exceeds a predetermined threshold level set by said threshold circuit.

2. A carrier recovery circuit according to claim 1, including a regenerated carrier processor disposed between the carrier regeneration circuit and said delay means, said regenerated carrier processor being operative to effect frequency conversion or division of the carrier component extracted by the carrier regeneration circuit, one of the input and output of the regenerated carrier processor being coupled to the input of the frequency detector.

3. A demodulated data compensator comprising:

a carrier regeneration circuit for extracting the regenerated carrier component from an input digital PSK wave,

a regenerated carrier processor for converting the output of said carrier regeneration circuit into a recovered carrier,

a detector for obtaining demodulated data as a result of detection of said input digital PSK wave by using the recovered carrier from said regenerated carrier processor,

a memory device coupled to said detector for temporarily storing said demodulated data,

a converter coupled to said memory device for reversing the polarity of the data read out of the memory device and/or for exchanging one item of data for another,

a frequency detector for detecting the instantaneous value of the frequency of one of said recovered and regenerated carriers,

an integrator for integrating the output of said frequency detector, and a threshold circuit coupled to said integrator and having an output which is coupled to said converter, said threshold circuit being operative, when the level of said integrator output exceeds a predetermined threshold level set by said threshold circuit and indicative of the occurrence of phase slip, to control said converter to reverse the polarity of the demodulated data read out of said memory device and/or exchanging items of data from said memory device with one another according to a predetermined rule, thereby compensating an error in said demodulated data caused by the phase slip.