Carrier and test socket for leadless integrated circuit

• US 4,329,642 A
• Filed: 03/09/1979
• Issued: 05/11/1982
• Est. Priority Date: 03/09/1979
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Williams, Clair E., Luthi, Robert B.
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US06/018,869
• Time in Patent Office: 1,159 Days
• Field of Search: 324/158 F, 324/158 P, 339/17 R, 339/17 C, 339/17 CF, 339/174, 174/52 FP
• US Class Current: 324/754.08
• CPC Class Codes: G01R 1/0483 Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips for IC's with connecting points around the edges only G01R1/0433
• CPC Class Codes: H05K 7/1023 co-operating by abutting, e.g. flat pack

Abstract

A carrier and test socket for a leadless integrated circuit package includes a base portion having a cavity for receiving the integrated circuit and a plurality of leads on a surface and extending from the cavity. The leads are arranged to mate with contacts of test equipment, and a portion of each lead is cantilevered into the cavity and arranged to mate with contacts of the integrated circuit. The carriers are configured to facilitate stacking, and a retainer member is provided for retaining the integrated circuit in the carrier while being individually handled.

Claims

1. A leadless integrated circuit carrier and test socket comprising a base, a circuit receiving cavity disposed in a central portion of said base, a plurality of electrically conductive leads disposed on a major surface of said base and affixed thereto, said body leads arranged to mate with contacts of test means, a cantilever portion of each of said leads projecting into said cavity, each of said cantilever portions including a contact area with the contact areas cooperatively arranged to mate with contacts on said integrated circuit means for retaining an integrated circuit in said cavity and in pressure contact with said cantilever portions of said leads, the top surface of said base having a raised portion, the bottom surface of said base having a recessed portion whereby a plurality of carriers and sockets can be stacked with the raised portion of one carrier and socket mating with the recessed portion of an adjacent carrier and socket.

2. A carrier and test socket as defined in claim 1 wherein said bottom surface includes guide means for reception by automated production equipment.

3. A carrier and test socket as defined by claim 2 wherein at least two sides thereof include notches to facilitate alignment of said carrier and socket with test equipment.