VMOS/Bipolar power switching device

• US 4,329,705 A
• Filed: 05/21/1979
• Issued: 05/11/1982
• Est. Priority Date: 05/21/1979
• Status: Expired due to Term

• Current Assignee: Exxon Research and Engineering Company (Exxon Mobil Corporation)
• Original Assignee: Exxon Research and Engineering Company (Exxon Mobil Corporation)
• Inventors: Baker, Richard H.
• Primary Examiner(s): LARKINS, WILLIAM
• Application Number:
  US06/040,991
• Time in Patent Office: 1,086 Days
• Field of Search: 357/23, 357/55, 357/60, 357/43, 357/46
• US Class Current: 257/330
• CPC Class Codes: H01L 27/0716 in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H03K 17/567 Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT

Abstract

A relatively high power switching device is provided via the combination on a common substrate of a VMOS transistor having a gate electrode for receiving a control signal, a drain electrode, and a source electrode, individually connected to the collector and base electrodes of a bipolar transistor, respectively, the collector-emitter current path of the latter being the main current carrying path of the switching device.

Claims

1. An integrated, high-speed, semiconductor power switching device, comprising:

a substrate;

a first layer of a first conductivity type overlying one face of said substrate;

a second layer of a second conductivity type extending into one region of said first layer;

a third layer of said first conductivity type extending into said second layer;

a first V-groove extending through central portions of said second and third layers into at least said first layer;

a fourth layer of said second conductivity type extending into another region of said first layer;

a fifth layer of said first conductivity type extending into said fourth layer;

a sixth layer of electrically insulative material overlying said first through fifth layers, and said first V-groove;

a first electrode overlying said sixth layer above said first V-groove;

a second electrode overlying and electrically contacting the other face of said substrate;

a third electrode extending through said sixth layer for electrically contacting said fifth layer;

a fourth electrode overlying and extending through said sixth layer over said second, third, and fourth layers, for electrically connecting these latter three layers together;

said first, second, third, and sixth layers, said substrate and said first V-groove, forming a vertical MOSFET device;

said first, fourth and fifth layers, and said substrate forming a vertical bipolar device;

said switching device being responsive to a voltage bias applied to said first electrode for establishing a low impedance channel for conducting current from said second electrode only vertically through said substrate, first, second, and third layers, into said fourth electrode, therefrom into said fourth and fifth layers to said third electrode, creating negative feedback between said second and fourth electrodes, and causing transistor action resulting in, and a much greater magnitude of, vertical current flow through said substrate, and said first, fourth, and fifth layers between said second electrode and said third electrode, said negative feedback providing means for preventing said vertical bipolar device from conducting in a saturated state;

said switching device being reponsive to a zero bias applied to said first electrode, for substantially raising the impedance of said channel and preventing current flow between said substrate and said first through fifth layers; and

a second V-groove extending into at least said first layer, said second V-groove being located between said second and fourth layers;

said sixth layer of electrical insulative material also overlying said second V-groove;

said fourth electrode overlying said sixth layer over said second V-groove.

2. The switching device of claim 1, wherein said first layer consists of an epitaxial layer.

3. An integrated, high-speed, high-power semiconductor switching device capable of dissipating at least 200 watts comprising:

a semiconductor substrate of a first conductivity type having two faces;

a first semiconductor region of said first conductivity type overlying one of said faces;

second and third non-contiguous semiconductor regions of a second conductivity type, opposite said first conductivity type, overlying said first region;

a fourth semiconductor region of said first conductivity type overlying said second region, said second region separating said fourth region from said first region;

a first V-groove overlying and extending through central portions of said second and fourth regions into at least said first region;

a fifth semiconductor region of said first conductivity type overlying said third region, said third region separating said fifth region from said first region;

a sixth region of electrically isolative material overlying said first through fifth regions, and said first V-groove;

a first electrode overlying said sixth region above said first V-groove;

a second electrode electrically contacting the other of said faces of said substrate;

a third electrode extending through said sixth region and electrically contacting said fifth region;

a fourth electrode, electrically interconnecting said second, third, and fourth regions, said fourth electrode extending through said sixth region to electrically contact said second, third and fourth regions, and overlying said sixth region to electrically interconnect said second, third and fourth regions;

resistive means connected between said third and fourth electrodes for providing a relatively low impedance current path therebetween;

said substrate, first, third, and fifth regions (collector to emitter current path) including first means for conducting at least 40 amperes of current therethrough with voltage levels of about 5 volts between said second and third electrodes;

said substrate, first, second and fourth regions including second means for selectivity conducting current from said second electrode through said substrate, first, second, and fourth regions, into said fourth electrode in response to a first selectivity variable voltage with respect to said fourth electrode, applied to said first electrode, and means for preventing current flow between said second and fourth electrodes in response to a second voltage, with respect to said fourth electrode, applied to said first electrode;

said substrate, first, third, and fifth regions including third means for selectively conducting current from said second electrode through said substrate, first, third, and fifth regions, into said third electrode in response to the variable current flowing from said fourth electrode through said third and fifth regions to said third electrode, for preventing current from flowing from said second to said third electrodes when current does not flow from said fourth electrode, through said third and fifth regions, to said third electrode, said substrate, first, third, and fifth regions and third means forming a bipolar transistor, said resistive means providing for rapid recombination of carriers stored within said third and fifth regions; and

said second means including fourth means for prohibiting said bipolar transistor from saturation;

a second V-groove extending into at least said first semiconductor region, said second V-groove being located between said second and third regions;

said sixth region of electrical insulative material also overlying said second V-groove;

said fourth electrode overlying said sixth region over said second V-groove.

4. A semiconductor switching device comprising:

a semiconductor substrate of a first conductivity type having two faces;

a first layer of a second conductivity type overlying one face of said substrate;

a gate V-groove extending at least into the first layer;

a first electrically insulative thin film coating the surfaces of the gate V-groove;

first and second diffusion regions of a third conductivity type extending into said first layer and located on opposite sides of and in contact with said V-groove;

third and fourth diffusion regions of said first conductivity type wholly within and extending into said first and second diffusion regions, respectively, each one of said third and fourth diffusion regions being in contact with said V-groove;

a fifth diffusion region of said third conductivity type extending into said first layer;

a sixth diffusion region of said first conductivity type surrounded by and extending into said fifth diffusion region;

an isolation V-groove extending at least into said first layer between said second and fifth diffusion regions;

a second electrically insulative thin film coating the surfaces of said isolation V-groove;

first electrically conductive means overlying said second electrically insulative thin film, and portions of said second, fourth, and fifth diffusion regions, for electrically interconnecting these diffusion regions;

second electrically conductive means overlying the other face of said substrate;

third electrically conductive means overlying said first insulative film over said gate V-groove;

fourth electrically conductive means overlying a portion of said sixth diffusion region; and

a third electrically insulative thin film coating overlying exposed areas around said electrically conductive means;

whereby in response to a voltage bias being applied to said third electrically conductive means, a low impedance path forms through said substrate, said first layer, and first through fourth diffusion regions, permitting current to flow from said second to said first electrically conductive means and therefrom into said fifth diffusion region, in turn causing the impedance between said substrate, first layer, and fifth and sixth diffusion regions to rapidly decrease from a relatively high to a relatively low value, permitting current to flow therethrough; and

whereby in response to a zero bias being applied to said third electrically conductive means, a relatively high impedance is formed between said substrate, first layers, and first through fourth diffusion regions, preventing current flow therefrom into said fifth region, causing a relatively high impedance to be established between said substrate, first layer, and fifth and sixth regions.

5. The semiconductor switching device of claim 4, wherein said first layer is an epitaxial layer.

6. An integrated, high-speed, high-power semiconductor switching device capable of dissipating at least 200 watts comprising:

a semiconductor substrate of a first conductivity type having two faces and having a relatively high majority carrier density;

a first semiconductor region of said first conductivity type overlying one of said faces and having a relatively low majority carrier density;

second and third non-contiguous semiconductor regions of a second conductivity type, opposite said first conductivity type, overlying said first region, said second and third regions having a relatively low majority carrier density;

a fourth semiconductor region of said first conductivity type overlying said second region, said second region separating said fourth region from said first region and having relatively high majority carrier density;

a first V-groove overlying and extending through central portions of said second and fourth regions into at least said first region;

a fifth semiconductor region of said first conductivity type overlying said third region, said third region separating said fifth region from said first region, said fifth region having a relatively high majority carrier density;

a sixth region of electrically isolative material overlying said first through fifth regions, and said first V-groove;

first electrode overlying said sixth region above said first V-groove;

a second electrode electrically contacting the other of said faces of said substrate;

a third electrode extending through said sixth region and electrically contacting said fifth region;

a fourth electrode electrically interconnecting said second, third, and fourth regions, said fourth electrode extending through said sixth region to electrically contact said second, third and fourth regions, and overlying said sixth region to electrically interconnect said second, third, and fourth regions;

said substrate, first, third, and fifth regions including first means for conducting at least 40 amperes of current therethrough with voltage levels of about 5 volts between said second and third electrodes;

said substrate, first, second, and fourth regions including second means for selectively conducting current from said second electrode through said substrate, first, second, and fourth regions, into said fourth electrode, in response to a first selectively variable voltage with respect to said fourth electrode, applied to said first electrode, and means for preventing current flow between said second and fourth electrodes in response to a second voltage, with respect to said fourth electrode, applied to said first electrode;

said substrate, first, third, and fifth regions including third means for selectively conducting current from said second electrode through said substrate, first, third, and fifth regions, into said third electrode in response to the variable current flowing from said fourth electrode through said third and fifth regions to said third electrode, for preventing current from flowing from said second to said third electrodes when current does not flow from said fourth electrode, through said third and fifth regions, to said third electrode, said substrate, first, third, and fifth regions and third means forming a bipolar transistor;

fourth means for providing a relatively low-impedance current path between said third and fifth regions for causing rapid recombination of carriers stored within these regions, thereby substantially reducing the turn-off time for said device; and

said second means including fourth means for prohibiting said bipolar transistor from saturating;

a second V-groove extending into at least said first semiconductor region, said second V-groove being located between said second and third regions;

said sixth region of electrical insulative material also overlying said second V-groove;

said fourth electrode overlying said sixth region over said second V-groove.

7. An integrated, high-speed, semiconductor power switching device comprising:

a substrate of a first conductivity type;

a first layer of said first conductivity type overlying one face of said substrate;

a second layer of a second conductivity type extending into one region of said first layer;

a third layer of said first conductivity type extending into said second layer;

a fourth layer of said second conductivity type extending into another region of said first layer;

a fifth layer of said first conductivity type extending into said fourth layer;

a sixth layer of electrically insulative material overlying said first through fifth layers;

a first electrode overlying said sixth layer at a position above said second layer such that the first electrode may be used to induce a channel along said second layer between the first and third layers;

a second electrode overlying and electrically contacting the other face of said substrate;

a third electrode extending through said sixth layer for electrically contacting said fifth layer;

a fourth electrode overlying and extending through said sixth layer over said second, third, and fourth layers, for electrically connecting these latter three layers together; and

an isolation V-groove extending at least into said first layer between the regions of said second and fourth layers.

8. The semiconductor switching device of claim 7, wherein said first layer is an epitaxial layer.

10. The switching device of claim 8 comprising a plurality of N said switching devices, N being an integer number greater than 1, said conductive means electrically connecting the gates of the VMOS transistors of said N devices in common and the collector-emitter current paths of the bipolar transistors thereof in parallel for providing about N times greater current switching capability relative to a single switching device.

11. The switching device of claim 8 comprising a plurality of N said switching devices, N being an integer greater than 1, the gates of the VMOS transistors of said N devices being receptive of individual control signals, and said conductive means electrically connecting the collector-emitter current paths of the bipolar transistors thereof in series for providing about N times greater voltage breakdown capability relative to a single switching device.

12. The switching device of claim 8, wherein said bipolar transistor includes at least a double-diffused epitaxial planar bipolar transistor.

13. The switching device of claims 8, wherein VMOS transistor includes at least a double-diffused epitaxial vertical metal oxide semiconductor.

9. A power switching device capable of being fabricated on a single semiconductor substrate comprising:

first, second, and third terminals;

a vertical metal oxide semiconductor (VMOS) field effect transistor having a gate, source, and drain electrodes;

a bipolar transistor having a base, emitter, and collector electrodes;

an isolation groove located on said substrate between said VMOS and bipolar transistors for providing isolation therebetween;

conductive means for electrically connecting said drain to said collector, said source to said base, said gate to said first terminal for receiving a first control signal, said emitter to said second terminal, and the common connection of said drain and collector to said third terminal;

means responsive to said first control signal and including the operating characteristics of said VMOS transistor for biasing said bipolar transistor within an operating range up to the edge of saturation; and

resistive means connected between said base and emitter electrodes for providing a relatively low impedance current path therebetween, for reducing the turn-off time of said device.

14. An integrated high-power solid-state switching circuit comprising:

first through third terminals;

a vertical metal oxide semiconductor (VMOS) field effect transistor having a gate electrode connected to said first terminal for receiving a control signal and a channel for conducting current;

a bipolar transistor having collector and emitter electrodes connected to said second and third terminals, respectively, and a base electrode, said channel of said VMOS transistor being connected between said collector and base electrodes;

feedback means including the characteristics of said VMOS transistor and its connection to the collector and base electrodes for biasing said bipolar transistor into equilibrium within an operating range up to the edge of saturation;

an isolation groove located between said VMOS and bipolar transistors for providing electrical isolation therebetween;

control means responsive to an input signal for producing said control signal at a voltage level for controlling the conduction of current between said second and third terminals; and

relatively low impedance resistance means connected between the base and emitter electrodes of said bipolar transistor, charge being accumulated between these electrodes during the conduction of said bipolar transistor, whereby said resistance means provides a discharge current path for this charge during the turn off cycle of said bipolar transistor initiated by turn off of said VMOS, thereby reducing the turn off time of said bipolar transistor.

15. In a switching device including a bipolar power switching transistor having base, collector, and emitter electrodes, wherein the bipolar transistor typically has d.c. input impedances ranging from 1.0 to 10.0 ohms, d.c. current gains from 10 to 50, and susceptibility to current hogging problems leading to thermal runaway, the improvement comprising:

a vertical metal oxide semiconductor (VMOS) field effect transistor having a gate electrode receptive of a control signal, a drain electrode connected to said collector electrode and receptive of an operating voltage, and a source electrode connected to said base electrode, the main current carrying path of said improved switching device being between the collector and emitter electrodes of said bipolar transistor, said improved device having a d.c. input impedance exceeding 10¹² ohms, and a d.c. current gain exceeding 10⁶, the transient capability of said bipolar transistor being improved by a factor of at least 4, said current hogging problems leading to thermal runaway being substantially eliminated, and said improved device having a switching response time to a pulse control signal that is at least about four times faster than said bipolar transistor alone, and an overall power dissipation therein that is substantially less than said VMOS transistor alone when conducting at comparable current levels;

a relatively low-value resistor connected between the base and emitter electrodes of said bipolar transistor, for providing a discharge path for charge in the base and emitter regions of said bipolar transistor, thereby reducing its turn-off time; and

said VMOS and bipolar transistors being formed side by side on the same substrate of a single semiconductor chip and electrically separated from one another by means of an isolation groove in said chip.

16. The improved switching device of claim 15, wherein said VMOS transistor consists of a double-diffused epitaxial vertical metal oxide semiconductor field effect transistor, and said bipolar transistor consists of a double-diffused epitaxial planar bipolar transistor.

17. A high-power solid-state switch consisting of a VMOS field effect transistor having a gate electrode receptive of a control signal, a drain electrode, and a source electrode, a bipolar transistor having a collector electrode connected to said drain electrode of said VMOS transistor and receptive of a first operating voltage, a base electrode connected to said source electrode of said VMOS transistor, and an emitter electrode, and means consisting of the characteristics of said VMOS transistor for providing direct feedback between the collector and base of said bipolar transistor for maintaining said bipolar transistor during operation in equilibrium within an operating range up to the edge of saturation, and

a low-value resistor connected between the base and emitter electrodes of said bipolar transistor, for reducing the turn-off time thereof, wherein said VMOS and bipolar transistors are formed side by side on the same substrate of a single semiconductor chip and are electrically separated from the other by means of an isolation groove in said chip.