Semiconductor read/write memory array having serial access

• US 4,330,852 A
• Filed: 11/23/1979
• Issued: 05/18/1982
• Est. Priority Date: 11/23/1979
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Rao, G. R. Mohan, Redwine, Donald J., White, Lionel S. Jr.
• Primary Examiner(s): Hecker, Stuart N.
• Application Number:
  US06/097,105
• Time in Patent Office: 907 Days
• Field of Search: 365/205, 365/219, 365/220, 365/221, 365/238, 365/239, 365/240
• US Class Current: 365/221
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1036 using data shift registers
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter

Abstract

A semiconductor memory device of the MOS/LSI type using dynamic one-transistor cells has a serial input/output system. A serial shift register having a number of stages equal to the number of columns in the memory cell array is connected to the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. Data from external is loaded serially into the shift register for a write operation, or serially shifted out of the register to external for a read operation. The cell array can be addressed for refresh during the time that data is being shifted into or out of the serial register.

Claims

1. A semiconductor memory device fabricated in a single integrated semiconductor circuit, comprising:

an array of rows and columns of dynamic read/write one-transistor memory cells employing MOS transistors and capacitors, with a bistable sense amplifier circuit for each column for input or output of data,

a serial register having a plurality of stages, each stage associated with a selected one of said columns;

transfer means for loading bits of data from the columns into the register stages or from the register stages into the columns in parallel in response to a transfer signal received from external to the device, the transfer means comprising a plurality of transfer gates connected between column lines and said stages;

means for receiving an address from a source external to the device and for addressing the array for selecting one of the rows for actuation by actuating the gates of all transistors in a row of said cells; and

means for loading a plurality of bits of data serially from said register to utilization means external to the device or from the utilization means to the register whereby a plurality of bits of data is accessed by one address.

2. A device according to claim 1 wherein timing means activates the loading of bits of data and the addressing the array, and wherein said timing means activates the addressing prior to loading when the data is loaded from columns to register or after the loading when the data is loaded from register to columns.

3. A semiconductor memory device fabricated in a single integrated semiconductor circuit, comprising:

an array of rows and columns of memory cells;

a plurality of separate output means each connected to one of the columns;

a serial input/output register having a plurality of stages, each stage associated with one of said columns via said output means;

means for loading the bits of data in the input/output register stages onto said columns in parallel and for loading bits of data from the columns into the input/output register stages in parallel in response to a transfer signal;

means for addressing the device for selecting one of the rows for actuation;

means for loading a plurality of bits of data serially into said input/output register or serially out of such register; and

timing means activating the loading of bits of data and the addressing of the array, the timing means activating the addressing prior to loading when the data is loaded from columns to register or after the loading when the data is loaded from register to columns.

4. A device according to claim 3 wherein the memory cells are of the one-transistor dynamic read/write, random access type, employing MOS transistors and capacitors.

5. A device according to claim 4 wherein a sense amplifier is located at the center of each column.

6. A device according to claim 5 wherein means are provided for actuating the sense amplifiers for refresh separately from said means for loading.

7. A device according to claim 6 wherein the sense amplifiers are bistable circuits with differential inputs separately from opposite column line halves.