Multiple data rate digital switch for a TDMA communications controller

• US 4,332,026 A
• Filed: 03/07/1980
• Issued: 05/25/1982
• Est. Priority Date: 03/07/1980
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Krug, Robert W., Brennen, John F., Alvarez, Joseph A. III
• Primary Examiner(s): BRITTON, HOWARD W
• Application Number:
  US06/128,322
• Time in Patent Office: 809 Days
• Field of Search: 370/104, 370/66, 455/12
• US Class Current: 370/347
• CPC Class Codes: H04B 7/212 Time-division multiple access [TDMA]
• CPC Class Codes: H04J 3/1647 Subrate or multislot multiplexing

Abstract

A multiple data rate digital switch for a TDMA communications controller is disclosed which can service a plurality of input/output ports having many different data rates on a time divided basis, either between ports connected to the same controller or between ports connected to different, geographically remote controllers. A transmit burst buffer and a receive burst buffer are connected between the local ports and a TDMA communication link and an intranodal buffer is connected between local ports. All three buffers are accessed by a switch control memory which stores n_i control words for each of the ports which are scanned m times per TDMA frame, there being a frame rate of f frames per second. Thus, the ports are selected and their data is buffered at a rate R_i which is equal to the product of n_i times m times f. In this manner, ports having a variety of data rates can be serviced on a time interleaved basis with maximum connectivity.

Claims

1. A multiple data rate digital switch for a TDMA communications controller having a plurality of input/output ports for transferring n_i channels of m data units each per TDMA frame from respective, local data users to a TDMA transmit burst communication link and transferring n_i of said channels of data from a TDMA receive burst communication link to said respective local users on a time interleaved basis during periodic TDMA frames, each port operating at its own data rate R_i, comprising:

a transmit burst buffer having a data input connected to a transmit bus common to the data outputs of all of said ports and a data output connected to said TDMA transmit burst communication link, with a plurality of addressable storage locations arranged into rows and m juxtaposed columns;

a receive burst buffer having a data input connected to said TDMA receive burst communication link and a data output connected to a receive bus common to the data inputs of all of said ports, with a plurality of addressable storage locations arranged into rows and m juxtaposed columns;

a scanner having a periodic cycle of m scans per TDMA frame, there being a frame rate of f frames per second, with a scan count output connected as a column address input to said transmit burst buffer and to said receive burst buffer;

a switch control memory, having an address input connected to a scan output of said scanner, a port select output connected to a control input to each of said ports and a stored address output connected to a row address input to said transmit burst buffer and to said receive burst buffer, for storing n_i control words for each of said ports, each of n_i controls words for the i-th port and issuing a port select signal to said i-th port and issuing a distinct row address to said transmit burst buffer and said receive burst buffer when scanned by said scanner, where n_i =R_i /mf;

whereby ports having a variety of data rates can be serviced on a time interleaved basis.

2. The apparatus of claim 1, which further comprises:

accessing means connected to said row address input of said transmit burst buffer, for reading out selected rows thereof during TDMA transmit bursting to said communication link.

3. The apparatus of claim 1 which further comprises:

an intranodal buffer having a data input connected to said transmit bus and a data output connected to said receive bus, with a plurality of addressable storage locations arranged into rows and two juxtaposed columns, with a row address input connected to said stored address output from said switch control memory and a column address input connected to said scan count output of said scanner, for transferring data between first and second ones of said ports.

4. The apparatus of claim 2, which further comprises:

a first and a second one of said ports having the same data rate R_i having n_i pairs of said control words in said switch control memory, each of said pairs having a first control word in the j-th pair issuing a port select signal to said first port and a row address to the p-th row in said intranodal buffer in even scans of said switch control memory and to the p+1 ST row in said intranodal buffer during odd scans and a second control word in said j-th pair issuing a port select signal to said second port and a row address to the p+1 ST row in said intranodal buffer in even scans of said switch control memory and to the p-th row in said intranodal buffer during odd scans.

5. The apparatus of claim 3, which further comprises:

said scan count connected to said column address input enabling a read access of a first one of said columns of said intranodal buffer and a write access of a second one of said columns of said intranodal buffer during even numbered ones of said scans of said switch control memory and enabling a read access of said second one of said columns of said intranodal buffer and a write access of said first one of said columns of said intranodal buffer during odd numbered ones of said scans of said switch control memory.

6. A multiple data rate digital switch for a TDMA communications controller having a plurality of input/output ports for transferring n_i channels of m data units each per TDMA frame from respective, local data users to a transmit bus and transferring n_i of said channels of data from a receive bus to said respective local users on a time interleaved basis during periodic TDMA frames, each port operating at its own data rate R_i, comprising:

an intranodal buffer having a data input connected to said transmit bus and a data output connected to said receive bus, with a plurality of addressable storage locations arranged into rows and two juxtaposed columns;

a scanner having a periodic cycle of m scans per TDMA frame, there being a frame rate of f frames per second, with a scan count output connected as a column address input to said intranodal buffer, addressing a first one of said columns during even numbered scans and addressing the second one of said columns during odd numbered scans;

a switch control memory having an address input connected to a scan output of said scanner, a port select output connected to a control input to each of said ports and a stored address output connected to a row address input to said intranodal buffer, for storing n_i control words for each of said ports;

a first and a second one of said ports having the same data rate R_i having n_i pairs of said control words in said switch control memory, each of said pairs having a first control word in the j-th pair issuing a port select signal to said first port and a row address to the p-th row in said intranodal buffer in even scans of said switch control memory and to the p+1 ST row in said intranodal buffer during odd scans and a second control word in said j-th pair issuing a port select signal to said second port and a row address to the p+1 ST row in said intranodal buffer in even scans of said switch control memory and to the p-th row in said intranodal buffer during odd scans;

whereby ports having a variety of data rates can be serviced on a time interleaved basis.

7. The apparatus of claim 6, which further comprises:

a transmit burst buffer having a data input connected to said transmit bus and a data output connected to a TDMA transmit burst communication link, with a plurality of addressable storage locations arranged into rows and m juxtaposed columns, with said scan count output from said scanner connected as a column address input and said stored address output of said switch control memory connected as a row address input, for transmitting n_i of said channels of data from respective, local data users to said TDMA transmit burst communication link.

8. The apparatus of claim 7, which further comprises:

accessing means connected to said row address input of said transmit burst buffer, for reading out selected rows thereof during TDMA transmit bursting to said communication link.

9. The apparatus of claim 8, which further comprises:

a receive burst buffer having a data input connected to a TDMA receive burst communication link and a data output connected to said receive bus, with a plurality of addressable storage locations arranged into rows and m juxtaposed columns, with said scan count output of said scanner connected as a column address input and said stored address of said switch control memory connected as a row address input for transferring n_i of said channels of data from said TDMA receive burst communication link to said respective local users on a time interleaved basis during periodic TDMA frames.

10. The apparatus of claim 9, which further comprises:

said TDMA transmit burst communication link and said TDMA receive burst communication link including a TDMA satellite transponder.