Multiple data rate digital switch for a TDMA communications controller
First Claim
1. A multiple data rate digital switch for a TDMA communications controller having a plurality of input/output ports for transferring ni channels of m data units each per TDMA frame from respective, local data users to a TDMA transmit burst communication link and transferring ni of said channels of data from a TDMA receive burst communication link to said respective local users on a time interleaved basis during periodic TDMA frames, each port operating at its own data rate Ri, comprising:
- a transmit burst buffer having a data input connected to a transmit bus common to the data outputs of all of said ports and a data output connected to said TDMA transmit burst communication link, with a plurality of addressable storage locations arranged into rows and m juxtaposed columns;
a receive burst buffer having a data input connected to said TDMA receive burst communication link and a data output connected to a receive bus common to the data inputs of all of said ports, with a plurality of addressable storage locations arranged into rows and m juxtaposed columns;
a scanner having a periodic cycle of m scans per TDMA frame, there being a frame rate of f frames per second, with a scan count output connected as a column address input to said transmit burst buffer and to said receive burst buffer;
a switch control memory, having an address input connected to a scan output of said scanner, a port select output connected to a control input to each of said ports and a stored address output connected to a row address input to said transmit burst buffer and to said receive burst buffer, for storing ni control words for each of said ports, each of ni controls words for the i-th port and issuing a port select signal to said i-th port and issuing a distinct row address to said transmit burst buffer and said receive burst buffer when scanned by said scanner, where ni =Ri /mf;
whereby ports having a variety of data rates can be serviced on a time interleaved basis.
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Abstract
A multiple data rate digital switch for a TDMA communications controller is disclosed which can service a plurality of input/output ports having many different data rates on a time divided basis, either between ports connected to the same controller or between ports connected to different, geographically remote controllers. A transmit burst buffer and a receive burst buffer are connected between the local ports and a TDMA communication link and an intranodal buffer is connected between local ports. All three buffers are accessed by a switch control memory which stores ni control words for each of the ports which are scanned m times per TDMA frame, there being a frame rate of f frames per second. Thus, the ports are selected and their data is buffered at a rate Ri which is equal to the product of ni times m times f. In this manner, ports having a variety of data rates can be serviced on a time interleaved basis with maximum connectivity.
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Citations
10 Claims
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1. A multiple data rate digital switch for a TDMA communications controller having a plurality of input/output ports for transferring ni channels of m data units each per TDMA frame from respective, local data users to a TDMA transmit burst communication link and transferring ni of said channels of data from a TDMA receive burst communication link to said respective local users on a time interleaved basis during periodic TDMA frames, each port operating at its own data rate Ri, comprising:
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a transmit burst buffer having a data input connected to a transmit bus common to the data outputs of all of said ports and a data output connected to said TDMA transmit burst communication link, with a plurality of addressable storage locations arranged into rows and m juxtaposed columns; a receive burst buffer having a data input connected to said TDMA receive burst communication link and a data output connected to a receive bus common to the data inputs of all of said ports, with a plurality of addressable storage locations arranged into rows and m juxtaposed columns; a scanner having a periodic cycle of m scans per TDMA frame, there being a frame rate of f frames per second, with a scan count output connected as a column address input to said transmit burst buffer and to said receive burst buffer; a switch control memory, having an address input connected to a scan output of said scanner, a port select output connected to a control input to each of said ports and a stored address output connected to a row address input to said transmit burst buffer and to said receive burst buffer, for storing ni control words for each of said ports, each of ni controls words for the i-th port and issuing a port select signal to said i-th port and issuing a distinct row address to said transmit burst buffer and said receive burst buffer when scanned by said scanner, where ni =Ri /mf; whereby ports having a variety of data rates can be serviced on a time interleaved basis. - View Dependent Claims (2, 3, 4, 5)
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6. A multiple data rate digital switch for a TDMA communications controller having a plurality of input/output ports for transferring ni channels of m data units each per TDMA frame from respective, local data users to a transmit bus and transferring ni of said channels of data from a receive bus to said respective local users on a time interleaved basis during periodic TDMA frames, each port operating at its own data rate Ri, comprising:
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an intranodal buffer having a data input connected to said transmit bus and a data output connected to said receive bus, with a plurality of addressable storage locations arranged into rows and two juxtaposed columns; a scanner having a periodic cycle of m scans per TDMA frame, there being a frame rate of f frames per second, with a scan count output connected as a column address input to said intranodal buffer, addressing a first one of said columns during even numbered scans and addressing the second one of said columns during odd numbered scans; a switch control memory having an address input connected to a scan output of said scanner, a port select output connected to a control input to each of said ports and a stored address output connected to a row address input to said intranodal buffer, for storing ni control words for each of said ports; a first and a second one of said ports having the same data rate Ri having ni pairs of said control words in said switch control memory, each of said pairs having a first control word in the j-th pair issuing a port select signal to said first port and a row address to the p-th row in said intranodal buffer in even scans of said switch control memory and to the p+1 ST row in said intranodal buffer during odd scans and a second control word in said j-th pair issuing a port select signal to said second port and a row address to the p+1 ST row in said intranodal buffer in even scans of said switch control memory and to the p-th row in said intranodal buffer during odd scans; whereby ports having a variety of data rates can be serviced on a time interleaved basis. - View Dependent Claims (7, 8, 9, 10)
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Specification