MOS Latch circuit

• US 4,333,020 A
• Filed: 05/23/1979
• Issued: 06/01/1982
• Est. Priority Date: 05/23/1979
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Maeder, Heinz B.
• Primary Examiner(s): Chatmon, Jr., Saxfield
• Application Number:
  US06/041,569
• Time in Patent Office: 1,105 Days
• Field of Search: 307/297, 307/200 B, 307/481, 307/291, 307/353, 307/451, 307/452, 307/453, 307/480, 307/279
• US Class Current: 327/212
• CPC Class Codes: H03K 3/356043 with synchronous operation

Abstract

A MOS latch circuit is provided which has a fast response and is sensitive to low level input clock signals. The latch circuit has two load devices which are connected to a pair of cross-coupled transistors. A controllable current source is used to control the current flow through the cross-coupled pair of transistors. A first coupling transistor is connected between the input of the cross-coupled pair of transistors and a second controllable current source. A second coupling transistor is connected between a second input of the cross-coupled pair of transistors and to the second controllable current source. The first and second coupling transistors are enabled by input data signals to the latch circuit while the first and second controllable current sources are controlled by clock signals.

Claims

1. A field effect transistor circuit having a first and a second voltage terminal, and capable of receiving a first and a second input comprising:

a first load transistor coupled between the first voltage terminal and a first node;

a second load transistor coupled between the first voltage terminal and a second node;

a pair of cross-coupled transistors coupled between a third node and the first and second nodes;

a first field effect transistor having a first and a second electrode and a gate electrode, the first electrode being coupled to the third node and the second electrode being coupled to the second voltage terminal, and the gate electrode being for receiving a first clock signal;

a second field effect transistor coupled between the first node and a fourth node and having a gate electrode for receiving the first input;

a third field effect transistor coupled between the second node and the fourth node and having a gate electrode for receiving the second input; and

a fourth field effect transistor coupled between the fourth node and the second voltage terminal and having a gate electrode for receiving a second clock signal.

2. The circuit of claim 1 wherein the first and second load transistors are depletion transistors.

3. A latch circuit having a cross-coupled pair of transistors;

a first and a second load device coupled to the cross-coupled pair of transistors;

a first controllable current source coupled to the cross-coupled pair of transistors;

a second controllable current source; and

a first and a second input transistor coupled from the cross-coupled pair of transistors to the second controllable current source.

4. A MOS latch circuit having a first and a second voltage terminal, comprising:

a first and a second load device, the first load device being coupled between a first node and the first voltage terminal, the second load device being coupled between a second node and the first voltage terminal;

a pair of cross-coupled transistors coupled between a third node and the first and second nodes;

a first controllable current source coupled between the third node and the second voltage terminal;

a second controllable current source coupled between a fourth node and the second voltage terminal;

a first coupling transistor having a first and second electrode and a gate electrode, the first electrode being coupled to the first node and the second electrode being coupled to the fourth node, and the gate electrode being coupled to a first input, and a second coupling transistor having a first and a second electrode and a gate electrode, the first electrode of the second coupling transistor being coupled to the second node, the second electrode of the second coupling transistor being coupled to the fourth node, and the gate electrode of the second coupling transistor being coupled to a second input.

5. The MOS latch circuit of claim 4 wherein the first and second controllable current sources are field effect transistors each having a gate electrode coupled to a first and a second clock input, respectively.

6. The MOS latch circuit of claim 5 wherein the first and second load devices are field effect transistors.

7. The MOS latch circuit of claim 4 wherein the first and second controllable current sources are operated in their linear operating region.