Method and apparatus for processing an analog signal

• US 4,333,024 A
• Filed: 10/18/1979
• Issued: 06/01/1982
• Est. Priority Date: 10/25/1978
• Status: Expired due to Term

• Current Assignee: Compagnie Internationale Pour L'Informatique Cii-Honeywell Bull
• Original Assignee: Compagnie Internationale Pour L'Informatique Cii-Honeywell Bull
• Inventors: Maussion, Daniel
• Primary Examiner(s): Miller, Jr., Stanley D.
• Assistant Examiner(s): Davis, B. P.
• Application Number:
  US06/085,959
• Time in Patent Office: 957 Days
• Field of Search: 307/351, 307/352, 307/360, 307/542, 307/494, 328/150, 328/151, 328/28
• US Class Current: 327/58
• CPC Class Codes: G06K 7/10851 Circuits for pulse shaping, amplifying, eliminating noise signals, checking the function of the sensing device basic electronic circuitry H03
• CPC Class Codes: G06V 10/28 Quantising the image, e.g. histogram thresholding for discrimination between background and foreground patterns
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: H03K 5/082 with an adaptive threshold

Abstract

A method and apparatus for processing an analog signal before it is converted into steep-sided pulses wherein a variable D.C. voltage is generated whose variation is representative of the change in values of the negative-going portions of the analog signal. A voltage summing means receives on the one hand the analog signal and on the other hand the variable D.C. voltage to provide steep-sided output pulses in synchronization with the "significant" portions of the analog signal.

Claims

1. A circuit for processing analog signals comprising generating means for generating a variable D.C. voltage and having an input connected to receive the said analog signals and an output for said variable D.C. voltage, said generating means comprising:

(a) a peak voltage following arrangement including a first differential amplifier having an inverting input connected to receive the said analog signals through a first capacitor connected to said generating means input, a noninverting input connected to receive a D.C. reference voltage, and an output, a second capacitor having one of its electrodes connected to a ground potential, a diode connected between the output of said first differential amplifier and the other electrode of said second capacitor to charge the latter, and a discharge circuit for the said second capacitor which, in conjunction with said second capacitor, defines a selected time constant, and

(b) an amplifier having an input connected to said other electrode of said second capacitor and an output connected to said output of said generating means, and voltage summing means having two inputs, one of which is connected to receive the said analog signals through said first capacitor and the other of which is connected to the output of said generating means, and an output for delivering a succession of steep-sided pulses responsive to analog signals applied to said circuit.

2. A circuit according to claim 1, wherein said voltage summing means includes a second differential amplifier, having an inverting input connected to said two inputs of the said voltage summing means via respective resistors and a non inverting input connected to receive said D.C. reference voltage.

3. A circuit according to claims 1 or 2, wherein said discharge circuit comprises a diode component having a non-linear characteristic, said component being connected between said other electrode of said second capacitor and said inverting input of said first differential amplifier to restrict the charge in the said second capacitor progressively for at least the highest amplitudes of the said analog signals.