Intelligent teletext decoder

• US 4,333,109 A
• Filed: 01/24/1980
• Issued: 06/01/1982
• Est. Priority Date: 01/24/1980
• Status: Expired due to Term

• Current Assignee: Zenith Radio Corporation (LG Corporation)
• Original Assignee: Zenith Radio Corporation (LG Corporation)
• Inventors: Ciciora, Walter S.
• Primary Examiner(s): NG, JIN FAY
• Application Number:
  US06/114,930
• Time in Patent Office: 859 Days
• Field of Search: 455/65, 358/160, 358/167, 358/147, 358/905, 375/14, 375/101
• US Class Current: 348/466
• CPC Class Codes: H04N 7/035 Circuits for the digital non-picture data signal, e.g. for slicing of the data signal, for regeneration of the data-clock signal, for error detection or correction of the data signal

Abstract

An equalizer and decoder system compensating for multipath distortion in digital format signals sent by teletext, for example. The system loads demodulated data signals and a received reference signal into a charge coupled device clocked in real time by a clock circuit. Later, the reference pulse is clocked to a microprocessor which determines tap coefficients for a transversal filter to correct the multipath distortion in the reference signal. The data signals are then applied to a transversal filter weighted with the calculated tap weights. After filtering, signals are decoded by the microprocessor.

In another embodiment a charge coupled device with tapped stages is used at one time for receiving the data signals in real time, and at a later time for part of a transversal filter.

In a simplest embodiment, distortions are removed by the microprocessor itself, without any separate transversal filter.

Claims

1. A combination automatic equalization and decoder system for a receiver which receives both transmitted digital format data signals and a transmitted reference signal, said system equalizing said digital data signals according to the distortion exhibited by said reference signal and decoding said data signals, comprising:

a time base expander having an input for receiving and moving said digital format data signals at a selectable rate to an output;

means including a microprocessor for determining the distortion exhibited by said reference signal and for operating on data signals inputted thereto to remove distortions therefrom based on said reference signal distortion;

means coupling said time base expander output to the input of said microprocessor; and

timing circuit means controllingly coupled to said time base expander and coupled to said microprocessor for regulating the rate at which said time base expander moves the data, said timing circuit means causing said time base expander to receive said transmitted digital format data signals at a first rate and later causing said data signals to move to said output at a slower second rate;

said microprocessor including means decoding and outputting said data signals.

2. The system according to claim 1 wherein said distortion removing means comprises an equalizer adjustably coupled to said microprocessor, said microprocessor being coupled to receive said reference signal and being coupled to cause said equalizer to remove distortions from said reference signal, said equalizer being coupled to receive data signals from said time base expander, whereby said equalizer adjusts said data signals in the same manner by which said reference signal is corrected.

3. The system according to claim 2 wherein said time base expander and said equalizer are combined in an integrated circuit having an input circuit and including:

(a) a tapped charge coupled device having a data input coupled to said input circuit;

(b) tap weight storage coupled to said input circuit;

(c) tap weighting circuits coupled to receive signals from said charge coupled device and said tap weight storage; and

(d) a summer coupled to receive signals from said tap weighting circuits;

said decoder including means coupling said summer output and said charge coupled device output to said microprocessor, said microprocessor being coupled to said input circuit.

4. The system according to claim 3 wherein said input circuit comprises:

input selection means controllably coupled to said microprocessor for selectively receiving tap weight signals from said microprocessor or said digital format data signals and for selectively routing selected ones of those signals to said charge coupled device or said tap weight storage.

5. The system according to claim 3 or 4 wherein said means coupling said summer output and said charge coupled device output to said microprocessor comprises an output selection switch controllably coupled to said microprocessor for selectively coupling signals outputted from said charge coupled device or said summer output to a data input of said microprocessor.

6. The system according to claim 1, 2, 3 or 4 further comprising a memory coupled to said microprocessor, said microprocessor storing decoded data in said memory for subsequent availability.

7. The system according to claim 1, 2, 3 or 4 wherein said means coupling said time base expander to said microprocessor includes an analog to digital converter.

8. The system according to claim 3 wherein said timing circuit means includes a clock driver circuit within said integrated circuit.

9. The system according to claim 2 wherein said equalizer comprises a transversal filter with selectable tap weights controllably coupled to said microprocessor.

10. The system according to claims 1 or 2 wherein said time base expander comprises a charge coupled device.

11. A combination multipath distortion compensator and decoder system for use in a receiver which receives transmitted digital format data signals and a transmitted reference signal, said system compensating all of the signals in accordance with the distortion in the received reference signal, comprising:

(a) microprocessor means having an associated memory for receiving said reference signal and for calculating tap weights for a transversal filter to compensate for the distortion in said received reference signal;

(b) a charge coupled device with a data output stage and with taps at stages thereof;

(c) tap weight storage means for receiving and storing tap weights calculated by said microprocessor means;

(d) input routing means coupled to said microprocessor means for routing said calculated tap weights to said tap weight storage, and for routing data signals inputted to said combination system to said charge coupled device;

(e) tap weighting circuits coupled to receive data signals from said taps and coupled to receive tap weights from said tap weight storage for weighting data signals in accordance with tap weights;

(f) summing means for receiving and summing said weighted data signals;

(g) means coupling the output of said summing means and said data output stage to said microprocessor means;

(h) clock circuit means coupled to said charge coupled device for clocking data into and out of said charge coupled device at selected rates;

said clock circuit clocking said data signals into said charge coupled device in real time and subsequently clocking said data signals out of said charge coupled device at a rate compatable with the data handling capabilities of said microprocessor means, whereby said microprocessor means receives said data signals and calculates said tap weights;

said microprocessor means also decoding data signals received from said summing means.

12. The system of claim 11 wherein said clock circuit means is further coupled to said microprocessor means, and said input routing means is controllably coupled to said microprocessor means, said clock circuit means and microprocessor means causing said charge coupled device to be used at one time period for time expansion and at a second time period for a transversal filter portion.