Switched-capacitor floating-inductor simulation circuit

• US 4,333,157 A
• Filed: 06/25/1980
• Issued: 06/01/1982
• Est. Priority Date: 06/25/1980
• Status: Expired due to Term

• Current Assignee: AG Communication Systems Corp. (Nokia Corporation)
• Original Assignee: GTE Automatic Electric Laboratories Incorporated
• Inventors: Lee, Man S.
• Primary Examiner(s): Ruggiero, Joseph F.
• Application Number:
  US06/162,981
• Time in Patent Office: 706 Days
• Field of Search: 364/802, 364/825, 333/214, 333/215, 333/109, 328/167, 307/109, 307/110
• US Class Current: 703/4
• CPC Class Codes: H03H 11/485 Simulating inductances using operational amplifiers
• CPC Class Codes: H03H 19/004 Switched capacitor networks

Abstract

This simulation circuit is a one-port network having a pair of nodes connected to inputs of first and second voltage followers that have associated switched capacitors alternately connected across them for being discharged and connected to an integrator for being charged to the output voltage on the latter. A third switched capacitor is alternately connected in series with the voltage follower outputs for sensing the input voltage applied to the nodes, and connected to the integrator where the input voltage is integrated and transferred to the first and second switched capacitors. A floating inductance L=T² C4/C1C3 is simulated across the nodes, where T is the reciprocal of the switching frequency, C1, C2 and C3 are the capacitances of associated switched capacitors, C1=C2, C4 is the capacitance in the integrator, and the circuit is characterized by the LDI transformation.

Claims

1. An integratable switched-capacitor floating-inductor simulation circuit comprising:

first and second nodes adapted for receiving an input voltage;

first and second voltage follower means having input terminals connected to said first and second nodes, respectively, and having output terminals across which the input voltage is established;

first, second and third capacitors having capacitances C1, C2, and C3;

integrator means including a fourth capacitor having a capacitance C4 associated therewith, and having an input and an output terminal; and

switch means associated with said first, second and third capacitors and being periodically operative in first and second switch states;

operation of said switch means in the first state electrically connecting said first and second capacitors across said first and second voltage follower means, respectively, for discharging these capacitors, and electrically connecting said third capacitor to the output terminal of at least one of said voltage follower means for charging said third capacitor with the output voltage thereof;

operation of said switch means in the second state electrically connecting said third capacitor to said integrator means for causing the latter to integrate the charge on said third capacitor and produce an output voltage that is proportional to the integral of the input voltage that is available on the output terminals of said voltage follower means, and electrically connecting said first and second capacitors to said integrator means for charging these two capacitors to the output voltage, whereby a switched-capacitor floating-inductor is simulated across said first and second nodes.

2. The circuit according to claim 1 wherein said switch means completes a cycle of operation in the two switch states every T seconds and f=1/T is the sampling frequency for the switched capacitors which is greater than the Nyquist rate.

3. The circuit according to claim 2 wherein the fourth capacitor is the integrating capacitor of said integrator means and the simulated inductance is representable as L=T² C4/C1C3, where C1=C2 and the circuit is characterized by the LDI transformation.

4. The circuit according to claim 2 wherein the output voltage of said integrator means is produced with respect to a ground reference potential, said switch means being operative in the second state for electrically connecting said first and second capacitors between the output terminal of said integrator means and ground for charging these capacitors to the output voltage.

5. The circuit according to claim 4 wherein said switch means is operative in the first switch state for connecting said third capacitor in series with the output terminals of said first and second voltage follower means for charging it with the voltage that is available at said first and second voltage follower means output terminals, and is operative in the second state for electrically connecting said third capacitor between ground and the input terminal of said integrator means.

6. The circuit according to claim 4 wherein said integrator means comprises a differential input operational amplifier having one input terminal electrically connected to ground, said fourth capacitor being electrically connected between the other input terminal and the output terminal of said differential amplifier, said switch means being operative in the second state for electrically connecting said third capacitor between ground and the other input terminal of said differential amplifier which is at a virtual ground potential for discharging said third capacitor into said fourth capacitor.

7. The circuit according to claim 4 wherein said switch means is operative in the first state for electrically connecting said third capacitor between the output terminal of said first voltage follower means and ground for charging it with the output voltage therebetween.

8. The circuit according to claim 7 wherein said switch means is operative in the second state for connecting said third capacitor between the output terminal of said second voltage follower means and the input terminal of said integrator means for causing said fourth capacitor to integrate the charge voltage on said third capacitor and the output voltage of said second voltage follower means.

9. The circuit according to claim 8 wherein said integrating means comprises a differential input operational amplifier having one input terminal electrically connected to ground, said fourth capacitor being electrically connected between the other input terminal and the output terminal of said amplifier, said switch means being operative in the second state for electrically connecting said third capacitor between the other input terminal of said amplifier and the output terminal of said second voltage follower means.

10. The circuit according to claim 4 wherein said integrator means is a voltage follower type integrator means, said switch means being operative in the first switch state for electrically connecting said third capacitor in series with the output terminals of said first and second voltage follower means for charging it with the input voltage that is available at these output terminals, and being operative in the second state for electrically connecting said third capacitor across said voltage follower integrator means for causing the latter to integrate the charge voltage on said third capacitor.

11. The circuit according to claim 10 wherein said integrator means comprises a third voltage follower means having an output terminal and having an input terminal that is electrically connected through said fourth capacitor to ground, said switch means being operative in the second switch state for electrically connecting said third capacitor between the input and output terminals of said third voltage follower means for causing said third capacitor to discharge into said fourth capacitor.

12. The circuit according to claim 4 which is implemented in integrated circuit form in which said first, second, third and fourth capacitors are integrated capacitors having the bottom plates thereof electrically connected to or switched between ground and virtual ground potentials, electrically connected to or switched between output terminals of a voltage source such as a voltage follower means, or electrically switched between ground and the output terminal of a voltage source for rendering the circuit substantially insensitive to parasitic capacitance effects associated with the bottom plates of said integrated capacitors.

13. The circuit according to claim 12 wherein said switch means comprises:

timing means providing continuous non-overlapping in-phase and out-of-phase timing control signals φ

1 and φ

2, said timing signals having a period T;

first and second integrated switching transistors having first terminals electrically connected to the top and bottom plate sides of said first capacitor and having second terminals connected to the input and output terminals of said first voltage follower means, respectively, and having control electrodes receiving the same one of said timing signals;

third and fourth integrated switching transistors having first terminals connected to the top and bottom plate sides of said first capacitor and having second electrodes electrically connected to ground and to the output terminal of said integrator means, respectively, and having control electrodes receiving the same other timing signal;

fifth and sixth integrated switching transistors having first terminals electrically connected to top and bottom plate sides of said second capacitor and having second electrodes electrically connected to the input and output terminals of said second voltage follower means, respectively, and control electrodes receiving the one timing signal; and

seventh and eighth integrated switching transistors having first electrodes electrically connected to the top and bottom plate sides of said second capacitor and second electrodes electrically connected to the output terminal of said integrator means and to ground, respectively, and control electrodes receiving the other timing signal.

14. The circuit according to claim 13 wherein said switch means further comprises ninth and tenth integrated switching transistors having first electrodes electrically connected to one and other sides of said third capacitor and having second electrodes electrically connected to the output terminals of said first and second voltage follower means, respectively, and having control electrodes receiving the first timing signal;

and eleventh and twelfth integrated switching transistors having first electrodes electrically connected to the one and other sides of said third capacitor and having second electrodes connected to ground and to the input terminal to said integrator means, respectively, and having control electrodes receiving the other timing signal;

said switching transistors being responsive to the timing signals for periodically connecting the first and second capacitors across associated voltage follower means when the third capacitor is connected across the outputs of the latter and the timing signals are of one phase, and for connecting the first and second capacitors between the output terminal of said integrator means and ground when said third capacitor is connected between the input terminal of said integrator means and ground and the timing signals are of the other phase.

15. The circuit according to claim 14 wherein said switching transistors are MOS FET transistors.

16. The circuit according to claim 4 wherein said switch means is operative in the first state for electrically connecting one and other sides of said first and second capacitors to the input and output terminals of associated voltage followers;

said switch means being operative in the second state for electrically connecting the one and other terminals of said first capacitor to ground and to the output terminal of said integrator means, respectively, and for electrically connecting the one and other sides of said second capacitor to the output terminal of said integrator means and to ground, respectively.

17. The circuit according to claim 16 wherein said first and second capacitors are integrated capacitors with bottom plates associated with the other terminals thereof;

said integrator means further comprising a voltage source type amplifier means having an output terminal connected to the output terminal of said integrator means for rendering the circuit substantially insensitive to parasitic capacitance effects associated with the bottom plates of said first and second integrated capacitors.