Microcomputer with branch on bit set/clear instructions

• US 4,334,268 A
• Filed: 05/01/1979
• Issued: 06/08/1982
• Est. Priority Date: 05/01/1979
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Thomas, James S., Boney, Joel F., Rupp, Edward J. II
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/035,138
• Time in Patent Office: 1,134 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/234
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/324 using program counter relative addressing

Abstract

A single-chip microcomputer comprises a central processor unit (100), a random access memory (110), a read only memory (120), internal timing circuitry including a timer counter (131), and three I/O data ports (140, 150, and 160). Included within the instruction set of the microcomputer are a branch on bit set instruction and a branch on bit clear instruction. The branch on bit set instruction is a three-byte instruction in which the first byte represents the op code including a designation of a particular bit to be examined, the second byte represents the address of a memory location in which the designated bit is to be examined, and the third byte represents an offset which when combined with the contents of the program counter designates a memory location to which a branch is to be taken if the designated bit is in fact set. For the branch on bit clear instruction, a branch is performed when the particular bit examined is determined not to be set. The branch on bit set and branch on bit clear instructions facilitate serial I/O operations by the microcomputer.

Claims

1. In a data processing system comprising a memory having a plurality of storage locations for storing data and instructions and a processor for executing such instructions, a method of executing a conditional branch instruction, said instruction comprising an op code and a bit number, a first address portion designating a first storage location in said memory, and a second address portion designating a second storage location in said memory, said method comprising the steps of:

fetching the data stored in said first storage location using said first address portion of said instruction;

testing the state of the bit in the data fetched from said first storage location corresponding to said bit number; and

branching to said second storage location using said second address portion of said instruction if said bit is in a predetermined state.

3. The method of executing a conditional branch instruction as recited in claims 1 or 2, wherein said memory includes a storage location for storing information relating to the operation of at least one I/O device coupled to said data processing system.

4. The method of executing a conditional branch instruction as recited in claims 1 or 2, wherein said memory includes a random access memory.

5. The method of executing a conditional branch instruction as recited in claims 1 or 2, wherein said memory includes a read only memory.

6. The method of executing a conditional branch instruction as recited in claims 1 or 2, wherein said branching step is performed only if said bit is set.

7. The method of executing a conditional branch instruction as recited in claims 1 or 2, wherein said branching step is performed only if said bit is clear.

8. The method of executing a conditional branch instruction as recited in claims 1 or 2, wherein said data processing system is a microcomputer.

2. In a data processing system comprising a memory for storing data and instructions in a plurality of storage locations therein, and a processor for executing instructions in said memory addressed by a program counter portion thereof, a method of executing a conditional branch instruction, said instruction comprising an op code, a bit number, an address portion designating a first storage location in said memory, and an offset, said method comprising the steps of:

fetching the data stored in said first storage location using the address portion of said instruction;

testing the state of the bit in the data fetched from said first storage location corresponding to said bit number;

combining said offset with the contents of said processor program counter to provide a branch address; and

branching to a second storage location using said branch address if said bit is in a predetermined state.

9. In a data processing system comprising a memory having a plurality of storage locations for storing data and instructions and a processor for executing such instructions, said processor including a program counter, an instruction decoding and control unit, and an arithmetic logic unit, the improvement wherein said memory includes a first storage location for storing a conditional branch instruction, said conditional branch instruction comprising an op code and a bit number, a first portion designating a second storage location in said memory, and a second portion designating an offset, wherein said instruction decoding and control unit, responsive to said op code and said first portion of said conditional branch instruction, locates said second storage location, wherein said arithmetic logic unit, responsive to said bit number, provides a control signal if the bit in said second storage location corresponding to said bit number is in a predetermined state, and wherein said arithmetic logic unit, responsive to said control signal, combines said offset with the contents of said program counter to provide a memory address, whereby if said bit is in said predetermined state a branch is made to the location in said memory specified by said memory address.

10. The data processing system as recited in claim 9, wherein said data processing system is a microcomputer.

11. In a data processing system comprising a single-chip integrated circuit microcomputer including a memory having a plurality of storage locations for storing data and instructions and a processor for executing such instructions, said processor including a program counter, an instruction decoding and control unit, and an arithmetic logic unit, the improvement wherein said memory includes a first storage location for storing a conditional branch instruction, said conditional branch instruction comprising an op code and a bit number, a first portion designating a second storage location in said memory, and a second portion designating an offset, wherein said instruction decoding and control unit, responsive to said op code and said first portion of said conditional branch instruction, locates said second storage location, wherein said arithmetic logic unit, responsive to said bit number, provides a control signal if the bit in said second storage location corresponding to said bit number is in a predetermined state, and wherein said arithmetic logic unit, responsive to said control signal, combines said offset with the contents of said program counter to provide a memory address, whereby if said bit is in said predetermined state, a branch is made to the location in said memory specified by said memory address.

12. The data processing system as recited in claims 9 or 11, wherein said memory includes a storage location for storing information relating to the operation of at least one I/O device coupled to said data processing system.

13. The data processing system as recited in claims 9 or 11, wherein said memory includes a random access memory.

14. The data processing system as recited in claims 9 or 11, wherein said memory includes a read only memory.