Electronic control system

• US 4,335,448 A
• Filed: 04/06/1981
• Issued: 06/15/1982
• Est. Priority Date: 02/21/1979
• Status: Expired due to Fees

• Current Assignee: Tanknology/Engineered Systems, Inc.
• Original Assignee: Engineered Systems Incorporated
• Inventors: VanNess, Bradford O.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/251,310
• Time in Patent Office: 435 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/119, 364/465, 364/478, 364/479, 222/2, 222/26, 371/15, 371/22, 371/62, 235/92 AC, 235/92 FL, 235/381
• US Class Current: 710/241
• CPC Class Codes: G06F 13/22 using successive scanning, e.g. polling G06F13/24 takes precedence
• CPC Class Codes: G06Q 20/342 Cards defining paid or billed services or quantities
• CPC Class Codes: G07F 13/025 wherein the volume is determined during delivery
• CPC Class Codes: G07F 7/025 by means, e.g. cards, providing billing information at the time of purchase, e.g. identification of seller or purchaser, quantity of goods delivered or to be delivered
• CPC Class Codes: Y04S 50/12 Billing, invoicing, buying or selling transactions or other related activities, e.g. cost or usage evaluation

Abstract

An electronic control system particularly suited for use with an automatic fuel dispensing system uses a centrally located computer to supply serial polling signals to various sub-stations. At the sub-stations, the polling signals are decoded into signals used to control the operation of specific system relays operated by the system. The status of the decoded polling signals as well as the operating status of the relays is supplied back to the computer for verification. A time-out control circuit continuously monitors the input polling signals applied to the relay terminal. If activity does not appear on the input signal line at the terminal after a pre-established time interval, all of the system relays at that terminal are turned off or rendered inoperative, irrespective of the status of the relay control signal obtained from the output of the polling signal decoding circuit. As a consequence, if the remotely located computer should fail to properly operate for any reason, the system is placed in a "fail-safe" standby condition of operation.

Claims

1. An electronic control system having a central source of control and polling signals interconnected with a plurality of controlled terminal locations, the controlled terminal locations including in combination:

utilization circuit means at each controlled terminal location identified by a unique polling signal and having a control signal input terminal and responsive to signals applied thereon to be selectively rendered operative or inoperative thereby;

polling signal decoder means at each controlled terminal location for said utilization circuit means and having an input and at least one output terminal, and responsive to the unique polling signal identifying the controlled terminal location in which said polling signal decoder means is located when such unique polling signal is applied to the input terminal of said polling signal decoder means to produce an output signal on the output terminal thereof;

driver circuit means at each controlled terminal location connected between the output terminal of said polling signal decoder means and the input terminal of said utilization circuit means for such terminal location to selectively render said utilization circuit means operative or inoperative in response to the signals on the output terminal of said polling signal decoder means for such terminal location;

polling signal supply means coupled to the input terminals of all of said polling signal decoder means for applying polling signals thereto from the central source; and

separate control circuit means at each controlled terminal location coupled to receive signals from said polling signal supply means and coupled to one of said driver circuit means and said utilization circuit means at such controlled terminal location for rendering said utilization circuit means at only such controlled terminal location inoperative in response to the absence of the receipt of polling signals by such control circuit means for a predetermined time interval from said polling signal supply means;

each of said control circuit means at each of said controlled terminal locations operating independently of the control circuit means at other controlled terminal locations.

2. The combination according to claim 1 further including additional circuit means in each controlled terminal location, said additional circuit means coupled with at least said polling signal decoder means at the same controlled terminal location for supplying signals to the central source of control and polling signals indicative of the state of operation of said polling signal decoder means for such controlled terminal location.

3. The combination according to claim 2 wherein said additional circuit means is further coupled with the output of said driver circuit means for supplying signals representative of the state of the output of said driver circuit means to the source of control and polling signals.

4. The combination according to claim 1 wherein each of said control circuit means comprises a time-out circuit;

and further including a source of clock pulses coupled to said time-out circuit for causing said time-out circuit to produce a reset signal on the output thereof after a predetermined time interval, the output of said time-out circuit being connected to said one of said driver circuit means and said utilization circuit means at the controlled terminal location at which said control circuit means is located for rendering said utilization circuit means inoperative whenever said reset signal appears, said time-out circuit having a reset input coupled with said polling signal supply means for resetting said time-out circuit in response to the presence of polling signals from said polling signal supply means to prevent reset pulses from appearing on the output of said time-out circuit.

5. The combination according to claim 4 wherein said time-out circuit is coupled with said driver circuit means.

6. The combination according to claim 1 wherein said polling signal decoder means at each of controlled terminal locations has a plurality of output terminals;

and further including a plurality of utilization circuit means; and

a plurality of driver circuit means, each driver circuit means comprising binary latch circuit means operated in response to signals appearing on different output terminals of said decoder means for selectively rendering operative and inoperative the utilization circuit means connected to said binary latch circuit means.

7. The combination according to claim 6 wherein said control circuit means comprises a time-out circuit means;

and further including a source of clock pulses coupled to said time-out circuit means for causing said time-out circuit means to produce a reset output pulse on the output thereof after a predetermined time interval, said time-out circuit means having a reset input coupled to said polling signal supply means to cause said time-out circuit means to be reset in response to the presence of polling signals which normally occur at time intervals less than said predetermined time interval; and

means coupling the output of said time-out circuit means to said driver circuit means to render said utilization circuit means inoperative whenever said reset output pulse is produced by said time-out circuit means.

8. The combination according to claim 7 wherein the output of said time-out circuit means is coupled with reset inputs of all of said driver circuit means at only the controlled terminal location in which said time-out circuit means is located for causing the output of said driver circuit means to render all of said utilization circuit means at such controlled terminal location inoperative in response to the occurrence of a reset pulse from said time-out circuit, irrespective of the state of the signals applied to said binary latch circuit means by said polling signal decoder means.

9. The combination according to claim 8 further including additional circuit means coupled with at least said polling signal decoder means, and having an output connected to said source of polling signals, for supplying signals representative of the operation of said polling signal decoder means to said source of control and polling signals.

10. The combination according to claim 9 wherein said additional circuit means is further coupled with the output of said binary latch circuit means for supplying signals to said source of control and polling signals representative of the state of operation of said binary latch circuit means.