Recursive-type digital filter with reduced round-off noise
First Claim
1. In a recursive-type digital filter having a calculating means for calculating an output signal yn, and a first means for supplying said calculating means with at least an m-bit input signal xn of ##EQU14## one bit by one bit;
- and second means including a data conversion means which cooperates with said calculating means to delay by one sample period said output signal yn, and a feedback means for feeding back one bit by one bit to said calculating means at least an m-bit output signal yn-1 of ##EQU15## wherein M and N are positive integers which represent a delay of the signal transmission and wherein the respective signals received by said calculating means from said first and said feedback means are multiplied by corresponding weighting coefficients ak and bk in order to produce at every sampling period a (m+l)-bit data yn satisfying, ##EQU16## and ak and bk represent coefficients with aM, bN ≠
0 with the upper m-bits of said data yn being serially outputted as an output signal corresponding to said input signal xn from said filter, wherein the improvements comprises;
third means including a second data conversion means which cooperates with said calculating means to delay by one sampling period at least one of the lower l bits of said data yn and outputting a y'"'"'n-1 signal, andfourth means receiving said y'"'"'n-1 signal and outputting one bit by one bit to said calculating means a y'"'"'n-k signal so that said calculating means supplements said yn data by adding the product of said bk coefficient and the signal received from said fourth means, whereby said y'"'"'n-k signal, which is delayed by k sampling periods from said input signal xn, reduces round off errors.
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Abstract
A recursive-type digital filter comprising a calculation circuit. The calculation circuit is arranged to multiply an input signal including at least m-bit signal xn inputted at a predetermined sampling period and an output signal yn-k fed back to the input of the calculation circuit in accordance with the input signal xn after being subjected to a delay of k sampling periods by ak and bk coefficients corresponding to the filter characteristics, respectively, and then the products are added thereby to produce data yn of (m+l) bits satisfying, ##EQU1## and serially deliver the upper m-bit data of the data yn as an output signal corresponding to the input signal xn.
The filter further comprises a delay circuit for feeding back to the input of the calculation circuit a part of the round off data including the upper (m+1)th bit of the data yn so that the bk coefficient is multiplied by the fedback data of the upper (m+1)th bit and the product is added to the data yn, thereby to produce an output signal with reduced round off noise.
26 Citations
9 Claims
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1. In a recursive-type digital filter having a calculating means for calculating an output signal yn, and a first means for supplying said calculating means with at least an m-bit input signal xn of ##EQU14## one bit by one bit;
- and second means including a data conversion means which cooperates with said calculating means to delay by one sample period said output signal yn, and a feedback means for feeding back one bit by one bit to said calculating means at least an m-bit output signal yn-1 of ##EQU15## wherein M and N are positive integers which represent a delay of the signal transmission and wherein the respective signals received by said calculating means from said first and said feedback means are multiplied by corresponding weighting coefficients ak and bk in order to produce at every sampling period a (m+l)-bit data yn satisfying, ##EQU16## and ak and bk represent coefficients with aM, bN ≠
0 with the upper m-bits of said data yn being serially outputted as an output signal corresponding to said input signal xn from said filter, wherein the improvements comprises;third means including a second data conversion means which cooperates with said calculating means to delay by one sampling period at least one of the lower l bits of said data yn and outputting a y'"'"'n-1 signal, and fourth means receiving said y'"'"'n-1 signal and outputting one bit by one bit to said calculating means a y'"'"'n-k signal so that said calculating means supplements said yn data by adding the product of said bk coefficient and the signal received from said fourth means, whereby said y'"'"'n-k signal, which is delayed by k sampling periods from said input signal xn, reduces round off errors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- and second means including a data conversion means which cooperates with said calculating means to delay by one sample period said output signal yn, and a feedback means for feeding back one bit by one bit to said calculating means at least an m-bit output signal yn-1 of ##EQU15## wherein M and N are positive integers which represent a delay of the signal transmission and wherein the respective signals received by said calculating means from said first and said feedback means are multiplied by corresponding weighting coefficients ak and bk in order to produce at every sampling period a (m+l)-bit data yn satisfying, ##EQU16## and ak and bk represent coefficients with aM, bN ≠
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9. In a recursive-type digital filter having a calculation means for outputting an m-bit output signal yn and a first circuit for supplying a digital signal xn of m bits one bit by one bit to said calculation means, said digital signal xn being one which is sampled at a predetermined period, and a second circuit connected to said calculation means for delaying the signal yn by at least one sampling period and feeding back the delayed signal yn-k to said calculation means, said calculation means comprising a first multiplier for multiplying said yn-k signal by a bk coefficient of bits in accordance with the characteristics of said filter and providing (m+l)-th bit data, and a first adder for adding to said input signal xn the upper m bits of said (m+l) bit data from said first multiplier, thereby to produce serially the data yn having the upper m bits in accordance with said input signal xn and satisfying, ##EQU17## where N is a positive integer which represents a delay of the signal transmission, and bk, bN ≠
- 0, wherein the improvement comprises second calculation means for receiving at least one of the lower l-bits of said (m+l) bit data outputted from said first multiplier and outputting a signal y'"'"'n, a third circuit connected to said second calculation means for delaying said signal y'"'"'n by at least one sampling period and feeding back the delayed signal y'"'"'n-k to said second calculation means, said second calculation means comprising a second multiplier for multiplying said y'"'"'n-k signal by said bk coefficient, a second adder means for adding the lower m bits of the output of said first multiplier and the output of said second multiplier to produce said signal y'"'"'n and means for supplying the carry part of the output of said second adder to said first adder so that the carry part is added to said input signal xn together with the output of said first multiplier.
Specification