Backup power circuit for biasing bit lines of a static semiconductor memory

• US 4,337,524 A
• Filed: 02/07/1980
• Issued: 06/29/1982
• Est. Priority Date: 02/07/1980
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: Mostek Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Parkinson, Ward D.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/119,538
• Time in Patent Office: 873 Days
• Field of Search: 365/229, 371/66
• US Class Current: 365/189.09
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A circuit is provided for biasing the bit lines of a static semiconductor memory when each of the cells (150) within the memory is being powered by a backup power source due to failure of the primary power source. The bit lines (52) connected to the cells within the array (50) are connected to transistors (54) which bias the bit lines (52) to a high voltage upon detection of failure of the primary power for the computer. The bit lines (52) are maintained at a high voltage level to prevent discharge of a data storage node (156) through an access transistor (164) of a memory cell (150). Biasing of the bit lines (52) further prevents the integrated circuit substrate (150) from being driven excessively positive by capacitive coupling between the substrate (150) and the bit lines (52) when the primary power is restored to the circuit.

Claims

1. A circuit for utilizing a backup power source to prevent loss of the bit pattern stored in the memory cells of a static semiconductor memory upon failure of the primary power supplied thereto, the memory circuit having a plurality of control terminals for receiving control signals and the memory cells having bit lines for transferring information as voltage states to and from the memory cells, comprising:

means for detecting a failure of the primary power for the memory circuit,

means for connecting the backup power source to the memory cells through a selected one of the control terminals upon detection of the failure of the primary power, and

means for applying a predetermined voltage to each of the bit lines upon detection of the failure of the primary power, said predetermined voltage derived from the backup power source through said selected control terminal.

2. The circuit recited in claim 1 wherein said means for applying a predetermined voltage to each of the bit lines comprises a field effect transistor for each of the bit lines, the drain terminals of said transistors connected in common to said selected control terminal, the source terminals of said transistors connected to the respective bit lines and the gate terminals thereof connected to receive a voltage to render the transistors conductive upon detection of said primary power failure.

3. A method for utilizing a backup power souce to prevent loss of the bit pattern stored in the memory cells of a static semiconductor memory upon failure of the primary power supplied thereto, the memory circuit having a plurality of control terminals for receiving control signals and the memory cells having bit lines for transferring information as voltage states to and from the memory cells, comprising:

detecting a failure of the primary power for the memory circuit,

connecting the backup power source to the memory cells through a selected one of said control terminals upon detection of the failure of the primary power, and

applying a predetermined voltage to each of the bit lines upon detection of the failure of the primary power, said predetermined voltage derived from the backup power source through said selected control terminal.