Pace timing device

• US 4,337,529 A
• Filed: 05/23/1979
• Issued: 06/29/1982
• Est. Priority Date: 05/27/1978
• Status: Expired due to Term

• Current Assignee: Citizen Watch Co Limited (Citizen Electronics Company Limited)
• Original Assignee: Citizen Watch Co Limited (Citizen Electronics Company Limited)
• Inventors: Morokawa, Shigeru
• Primary Examiner(s): Miska, Vit W.
• Application Number:
  US06/041,564
• Time in Patent Office: 1,133 Days
• Field of Search: 368/3, 368/10, 368/12, 368/72-73, 368/107-111, 368/113-114, 368/121, 368/155-160, 368/250-251, 340/309.1, 340/309.4, 340/323, 340/384 E, 364/561, 364/569, 364/705, 364/710, 235/92 GA, 235/92 T
• US Class Current: 377/20
• CPC Class Codes: A61B 5/02438 with portable devices, e.g. worn by the patient
• CPC Class Codes: A61B 5/6826 Finger
• CPC Class Codes: A61B 5/6838 Clamps or clips
• CPC Class Codes: A61B 5/7405 using sound
• CPC Class Codes: A63B 2230/06 heartbeat rate only
• CPC Class Codes: A63B 69/0028 for running, jogging or speed-walking movable endless bands A63B22/02
• CPC Class Codes: A63B 71/0686 Timers, rhythm indicators or pacing apparatus using electric or electronic means
• CPC Class Codes: G04F 5/025 Electronic metronomes rhytem generation for electrophonic musical instruments G10H1/36

Abstract

A pace timing device for timing steps or other actions during physical exercise, providing audible tone bursts as timing information, and equipped with means for setting the repetition rate and rhythm of the tone bursts to suitable values. Audible and visible indications can be given of elapsed time and of numbers of actions completed during an exercise period, and pulse rate or other physiological parameters can be measured while exercise is being undertaken, and visible or audible indications thereof provided.

Claims

1. A combination of an electronic timepiece and pace timing device, comprising:

a source of a first frequency signal;

pace signal generation circuit means responsive to said first frequency signal for providing a pace signal;

an acoustic device responsive to said pace signal for providing an audible pace timing signal;

said first frequency signal source including a source of a timebase signal, externally operated frequency setting means, and synthesizer circuit means responsive to operation of said frequency setting means and to said timebase signal for producing a first frequency signal;

said pace signal generation circuit means including a frequency divider coupled to receive said timebase signal for thereby producing a carrier signal and time unit signal, and a modulator circuit for modulating said carrier signal by said first frequency signal to thereby produce a pace signal; and

a timekeeping counter circuit coupled to receive said time unit signal produced by said frequency divider circuit for thereby producing a time marker signal when a predetermined count of said time unit signal is attained, said time marker signal being applied to said modulator circuit to modulate said carrier signal for thereby producing a modulated time marker signal, said acoustic device being responsive to said modulated time marker signal for producing an audible time marker signal;

externally actuated switch means for selecting a timekeeping mode of operation and a pace timing mode of operation;

externally actuated switch means for selectively increasing and decreasing a pace timing signal frequency when said pace timing mode of operation is entered;

externally actuated switch means for initiating halting production of an audible pace timing signal when said pace timing mode of operation is entered;

display means for displaying current time and date when said timekeeping mode of operation is entered and for displaying an elapsed time when said pace timing mode of operation has been entered;

display means for indicating a pace timing signal frequency when said pace timing mode of operation is entered; and

display means for indicating a cumulative total of steps executed.

2. A pace timing device, comprising:

a source of a timebase signal;

externally operated frequency setting means;

synthesizer circuit means responsive to operation of said frequency setting means and to said timebase signal for producing a first frequency signal;

a frequency divider coupled to receive said timebase signal for thereby producing a carrier signal and time unit signal;

a modulator circuit for modulating said carrier signal by said first frequency signal to thereby produce a pace signal;

an acoustic device respective to said pace signal for producing an audible pace timing signal; and

a timekeeping counter circuit coupled to receive said time unit signal produced by said frequency divider circuit for thereby producing a time marker signal when a predetermined count of said time unit signal is attained, said time marker signal being applied to said modulator circuit to modulate said carrier signal for thereby producing a modulated time marker signal, said acoustic device being responsive to said modulated time marker signal for producing an audible time marker signal.

3. A pace timing device according to claim 2 wherein said frequency divider circuit produces a first carrier signal and a second carrier signal of differing frequencies, and wherein said first carrier signal is modulated by said first frequency signal in said modulator circuit to produce said pace signal and wherein said second carrier signal is modulated by said time marker signal to produce said modulated time marker signal.

4. A pace timing device according to claim 2 wherein said frequency divider produces a first carrier signal and a second carrier signal of differing frequencies, and wherein said second carrier signal is modulated by said time marker signal and the signal resulting from this modulation is applied to modulate said first carrier signal to produce said modulated time marker signal.

5. A pace timing device according to claim 2, and further comprising electro-optical display means for receiving said modulated time marker signal and for thereby providing a visible indication of an elapsed time.

6. A pace timing device according to claim 2, and further comprising a counter circuit and externally operated changeover switching means coupled to said counter circuit whereby said counter circuit is selectively caused to count said first frequency signal and a time unit signal produced by said frequency divider circuit in accordance with said changeover switching means, said counter circuit producing time marker signal when said time unit signal is counted and producing a step count signal when said first frequency signal is counted.

7. A pace timing device, comprising:

a source of a timebase signal;

externally operated frequency setting means;

a frequency synthesizer circuit responsive to operation of said frequency setting means and to said timebase signal for producing a first frequency signal;

a frequency divider coupled to receive said timebase signal, for thereby producing a carrier signal and a time unit signal;

a modulator circuit for modulating said carrier signal by said first frequency signal to thereby produce a pace signal; and

an acoustic device responsive to said pace signal for producing an audible pace timing signal; and

wherein said frequency synthesizer circuit comprises;

a counter circuit for counting pulses of said timebase signal;

memory means responsive to signals produced by said setting means for storing a numeric value;

comparator circuit means for comparing the count of said counter with said numeric value and for producing a first output signal when coincidence is detected between said count and said numeric value, and further, for producing a second output signal when a predetermined count of said counter circuit is attained;

a bistable circuit responsive to the first output signal from said comparator circuit for producing a first control signal and responsive to the second output signal from said comparator circuit for producing a second control signal; and

a gate circuit coupled to receive said timebase signal and responsive to said second control signal for passing said timebase signal to an output terminal and being furthermore responsive to said second control signal for inhibiting passage of said timebase signal to said .

8. A pace timing device, comprising:

a source of a timebase signal;

externally operated frequency setting means;

a frequency synthesizer circuit responsive to operation of said frequency setting means and to said timebase signal for producing a first frequency signal;

a frequency divider coupled to receive said timebase signal, for thereby producing a carrier signal and a time unit signal;

a modulator circuit for modulating said carrier signal by said first frequency signal to thereby produce a pace signal; and

an acoustic device responsive to said pace signal for producing an audible pace timing signal; and

wherein said frequency synthesizer circuit comprises;

a frequency divider circuit for dividing the frequency of said timebase signal;

a decoder circuit coupled to receive output signals from a plurality of stages of said frequency divider circuit and thereby generate weighted gating signals;

selection and memory circuit means responsive to signals produced by said setting means for selecting at least one of said weighted gating signals; and

a gate circuit for receiving said timebase signal and responsive to said selected weighting gate signal for passing said timebase signal to an output terminal.

9. A pace timing device, comprising:

a source of a timebase signal;

externally operated frequency setting means;

a frequency synthesizer circuit responsive to operation of said frequency setting means and to said timebase signal for producing a first frequency signal;

a frequency divider coupled to receive said timebase signal, for thereby producing a carrier signal and a time unit signal;

a modulator circuit for modulating said carrier signal by said first frequency signal to thereby produce a pace signal; and

an acoustic device responsive to said pace signal for producing an audible pace timing signal; and

wherein said frequency synthesizer circuit comprises;

a frequency divider circuit for dividing the frequency of said timebase signal;

a voltage-controlled oscillator circuit;

a counter circuit for counting an output signal of said voltage-controlled oscilltor circuit;

memory means responsive to signals produced by said setting means for storing a numeric value;

comparator means for comparing the count in said counter circuit with said numeric value, and for generating an output signal when coincidence is detected between said count and numeric value, said output signal being applied to said counter for causing the contents thereof to be reset to a count of zero; and

a phase detector circuit for comparing the phase of an output signal produced by said counter circuit and the phase of an output signal of said frequency divider circuit, and for producing a control signal indicative of a phase difference, said control signal being applied to said voltage-controlled oscillator to control the phase of the output signal thereof.

10. A pace timing device according to claim 9, wherein said voltage-controlled oscilaltor comprises a ring oscillator circuit.

11. A pace timing device according to claim 10, wherein said ring oscillator circuit comprises a plurality of complementary field effect transistor elements.

12. A pace timing device, comprising:

a source of a first frequency signal;

pace signal generation circuit means responsive to said first frequency signal for providing a pace signal;

an acoustic device responsive to said pace signal for providing an audible pace timing signal;

a step counter circuit for counting said first frequency signal and for producing a step count signal when a predetermined number of pulses of said pace signal have been counted;

means for detecting that the count in said step counter circuit has attained a value which is an integral multiple of a predetermined count value and for generating a control signal when such a count value is detected; and

means responsive to the contents of said step counter circuit and to said control signal for generating a step count repeater signal indicative of the value of said integral multiple.

13. A pace timing device according to claim 12, wherein said step count repeater signal comprises a single pulse when said detection means first detects that a count value equal to said predetermined count value has been attained by said step counter, and subsequently comprises a plurality of pulses generated each time that a value of said integral multiple of greater than one is detected, the number of said plurality of pulses being equal to said integral multiple.

14. A pace timing device according to claim 13, and further comprising a source of a carrier signal and modulation circuit means, said modulation circuit modulating said carrier signal by said step count repeater signal to generate a modulated step count repeater signal, and said acoustic device being responsive to said modulated step count repeater signal for producing an audible step count repeater signal.

15. A pace timing device according to claim 14, wherein said step counter circuit comprises a first and a second step counter circuit, and wherein

an output signal of said first step counter circuit is input to said second step counter circuit, said output signal being applied as a carry input signal to said second step counter circuit each time the count in said first step counter circuit has been incremented by said predetermined count value, and wherein said output signal of said first step counter constitutes said control signal.

16. A pace timing device according to claim 15, wherein said step count repeater signal generating means comprises:

a repeater signal counter circuit responsive to said control signal for being reset to a count of zero;

a gate circuit coupled to receive said first frequency signal and having an output terminal coupled to a clock input terminal of said repeater signal counter circuit,

comparator circuit means for comparing the count in said second step counter circuit with the count in said repeater signal counter circuit and for producing a coincidence detection circuit signal when coincidence is detected between said counts;

bistable circuit means responsive to said coincidence detection signal for being set to produce an output at a first logic level potential, said output being applied to an input of said gate circuit to enable said first frequency signal to be applied to said repeater signal counter when at said first logic level potential; and

a source of a reset signal, said reset signal being generated after a predetermined time interval following generation of said control signal and being applied to said bistable circuit means to thereby reset said bistable circuit means to generate an output signal at a second logic level potential, whereby said gate circuit is inhibited from passing said clock pulses to said repeater signal counter;

the output signal from said gate circuit constituting said step count repeater signal.

17. A pace timing device, comprising:

a source of a first frequency signal;

pace signal generation circuit means responsive to said first frequency signal for providing a pace signal;

an acoustic device responsive to said pace signal for providing an audible pace timing signal;

an elapsed time and step number counter circuit;

a source of a changeover control signal;

a source of a timebase signal;

frequency divider means for frequency dividing said timebase signal to provide a unit time signal;

changeover gate circuit means for receiving said unit time signal and said first frequency signal, being responsive to said changeover control signal for selectively applying said unit time signal and said first frequency signal to an input of said elapsed time and step number counter circuit;

carry control gate circuit means responsive to said changeover control signal for causing said elapsed time and step number counter circuit to count by a first count factor when said first frequency signal is applied to said elapsed time and step number counter circuit and to count by a second count factor when said unit time signal is applied to said elapsed time and step number counter circuit;

means for detecting that the count in said elapsed time and step number counter circuit has attained a count value which is an integral multiple of a predetermined count value and for generating a control signal when such a count value is detected; and

means responsive to the contents of said elapsed time and step number counter circuit and to said control signal for generating a step count and elapsed time repeater signal indicative of the value of said integral multiple.

18. A pace timing device according to claim 17, wherein said step count and elapsed time repeater signal comprises a single pulse when said detection means first detects that a count value equal to said predetermined count value has been attained by said elapsed time and step counter circuit, and subsequently comprises a plurality of pulses generated each time that a value of said integral multiple of greater than one is detected, the number of said pulses being equal to said integral multiple.

19. A pace timing device according to claim 18, and further comprising a source of a carrier signal and modulation circuit means, said modulation circuit means modulating said carrier signal by said step count and elapsed time repeater signal, to produce a modulated step count and elapsed time repeater signal, said acoustic device being responsive to said modulated step count and elapsed time signal for producing an audible step count and elapsed time signal.

20. A pace timing device, comprising:

a source of a first frequency signal and a timebase signal, said source including an oscillator circuit;

an operating switch coupled to an external operating member, for producing a single operating signal each time said operating member is actuated;

a bistable circuit responsive to said operating signal for being set to produce a first control signal;

a gate circuit coupled to said oscillator circuit to control the operation thereof, and responsive to said first control signal for enabling operation of said oscillator circuit;

frequency divider circuit means coupled to receive said timebase signal and produce a time unit signal;

timekeeping circuit means coupled to receive said time unit signal and to produce a terminating signal when a predetermined time has elapsed, said terminating signal being applied to a reset terminal of said bistable circuit to reset said bistable circuit, thereby causing said gate circuit to inhibit oscillation by said oscillator circuit;

pace signal generation circuit means responsive to said first frequency signal for providing a pace signal; and

an acoustic device responsive to said pace signal for providing an audible pace timing signal.

21. A pace timing device according to claim 20, wherein said operating switch is coupled to an input circuit comprising:

a resistor or relatively high value having one terminal connected to said input terminal and another terminal connected to a first logic level potential;

a field effect transistor having a drain electrode connected to said input terminal and a source electrode connected to said first logic level potential;

an inverter having an input terminal connected to said input terminal and an output terminal connected to a gate electrode of said field effect transistor;

whereby said input terminal is maintained in a low impedance condition at said first logic level potential when said operating switch is in an open condition, and wherein closing of said operating switch sets said input terminal to a second logic level potential, this transition between said first and second logic level potentials constituting said operating signal.

22. A pace timing device according to claim 20, and further comprising:

toggle-type bistable circuit means responsive to successive occurrences of said operating signal for producing an output signal which successively alternates between said first and second potentials;

drive circuit means coupled between said pace signal generation means and said acoustic device; and

control gate means coupled to said drive circuit means and responsive to the first potential state of said output signal from said toggle-type bistable circuit means for enabling said pace signal to be applied to said drive circuit and responsive to the second potential state of said output signal from said toggle-type bistable circuit means for inhibiting said pace signal from being applied to said drive circuit.

23. A pace timing device according to claim 21, and further comprising:

a first input control counter circuit responsive to said first potential state of said input terminal for being reset to a count of zero;

a first gate circuit coupled to receive a clock signal produced by said frequency divider circuit and having an output terminal coupled to an input terminal of said first input control counter circuit;

a second gate circuit coupled to output terminals of said first input control counter circuit and having an output terminal coupled to an input of said first gate circuit, whereby said first gate circuit is inhibited from passing said clock pulses to said first input control counter circuit when a predetermined count is attained in said first input control counter circuit, by an output signal from said second gate circuit, and is enabled to pass said clock pulses otherwise;

the output from said second gate circuit being applied to a reset terminal of said timekeeping circuit, whereby the contents of said timekeeping circuit are reset to zero when said predetermined count is attained by said first input control counter circuit.

24. A pace timing device powered by a battery, comprising:

a timebase oscillator circuit including a control gate circuit, oscillation by said timebase oscillator circuit being enabled when said control gate is in an inhibited condition and being enabled when said control gate is in an enabled condition;

a frequency divider comprising a counter circuit coupled to receive a timebase signal produced by said timebase oscillator circuit;

a first time counter circuit coupled to receive an output signal from said frequency divider counter circuit and therey produce a unit time signal;

a second time counter circuit coupled to receive said unit time signal and to thereby produce a time marker signal each time a first time interval has elapsed and to produce a termination signal when a second time interval has elapsed, said second time interval comprising an integral multiple of said first time interval;

an externally actuated digital switch for setting a code combination representing a numeric value, and comprising a plurality of electrical signals;

a comparator circuit for comparing said code combination with a count held in said frequency divider counter circuit, and for producing a coincidence signal when coincidence between said code combination and said count is detected;

a first gate circuit for detecting a predetermined count of said frequency divider counter circuit and for producing a detection signals when said count is detected;

a bistable circuit responsive to said detection signal for being reset to produce a first output signal, and responsive to said conicidence signal for being set to produce a second output signal;

a second gate circuit coupled to receive a first clock signal of relative high frequency from an input stage of said frequency divider counter circuit, being responsive to said first output signal for passing said first clock signal and being respnsive to said second output signal for inhibiting passage of said first clock pulses;

a pace signal counter for counting output signal pulses from said second gate circuit;

a third gate circuit coupled to receive output signals from said pace signal counter, for thereby producing a first frequency signal comprising a train of pulses having an average frequency determined by said code combination from said digital switch;

a rhythm signal counter coupled to receive an output signal from said pace signal counter and to produce an output signal coinciding with alternate successive pairs of pulses of said first frequency signal, said rhythm signal counter output signal being applied to said third gate circuit for inhibiting alternate successive pairs of pulses of said first frequency signal from being produced thereby;

a fourth gate circuit coupled between said rythm signal counter and said third gate means, for controlling application of said outlet signal of said rhythm signal counter to said third gate circuit;

a function control terminal comprising an externally controlled terminal, coupled to an input of said fourth gate circuit, whereby said output signal from said rhythm signal counter is enabled to be applied to said third gate circuit when said function control terminal is at a first potential and is inhibited from being applied when said function control terminal is at a second potential;

a modulator circuit coupled to receive said first frequency signal, said time marker signal, said termination signal, and carrier signals comprising third and fourth clock signals of relatively low frequency produced by said first time counter circuit, whereby said first frequency modulates said third clock signal to produce a pase timing signal, said time marker signal modulates said fourth clock signal and the resultant signal modulates said third clock signal to produce a modulated time marker signal, and said termination signal modulates said fourth frequency signal and the resultant signal modulates said third clock signal to produce a modulated terminal signal;

driver circuit means coupled to receive said pace signal, said modulated time marker signal, and said modulated termination signal and thereby produce drive signals;

an electrodynamic loudspeaker responsive to said drive signals for producing an audible pace timing signal, an audible time marker signal, and an audible termination signal;

an externally actuated operating switch, for producing a single operating signal comprising a transition from a first potential to a second potential when actuated;

a second bistable circuit responsive to said operating signal for being set to produce an operation enable signal, said operating enable control signal being applied to said control gate of said timebase oscillator circuit to enable oscillation thereof;

an input control counter circuit responsive to said second potential from said operating switch for being reset to a count of zero;

a fifth gate circuit coupled to receive a clock signal produced by said first time counter circuit and having an output terminal coupled to an input terminal of said input control counter circuit;

a sixth gate circuit coupled to output terminals of said input control counter circuit for detecting a predetermined count thereof, and having an output terminal coupled to an input of said fifth gate circuit, to inhibit said fifth gate circuit when said predetermined count is detected;

the output from said sixth gate circuit being applied to reset terminals of said second time counter circuit, whereby said second time counter circuit is reset when said predetermined count of said input control counter circuit is detected;

a timer control counter circuit responsive to said operating signal for being reset to a count of zero;

a seventh gate circuit coupled to receive a clock signal produced by said first time counter circuit, and having an output-terminal coupled to an input terminal of said timer control counter circuit; and

an eighth gate circuit coupled to output terminals of said timer control counter circuit for detecting a predetermined count thereof, and having an output terminal coupled to an input of said seventh gate circuit, to inhibit said seventh gate circuit when said prdetermined count is detected;

the output from said eighth gate circuit being applied to a control terminal of said modulator circuit, whereby said modulator circuit is enabled to produce said pace signal prior to said predetermined count of said timer control counter circuit being detected, and is inhibited from producing said pace signal after said predetermined count has been detected.

25. A pace timing device powered by a battery, comprising:

a timebase oscillator circuit including a control gate circuit;

a frequency divider comprising a counter circuit, coupled to receive a timebase signal produced by said timebase oscillator circuit;

a first time counter circuit coupled to receive an output signal from said frequency divider counter circuit, and thereby produce a unit time signal;

an externaly actuated operating switch for producing an operating signal;

a first bistable circuit responsive to said operating signal for being reset, to thereby produce an operation enable signal, said operation enable signal being applied to said control gate of the timebase oscillator circuit to enable oscillation thereof;

a first input control counter coupled to receive a clock signal from said first time counter circuit, said operating signal being coupled to control terminals of said first input control counter circuit to enable counting thereby;

a first gate circuit for detecting a predetermined count of said first input control counter, and for producing an output signal when said predetermined count is detected;

a second input control counter coupled to receive the output signal from said first gate circuit and to count successive occurrences of said output signal, counting by said second input control counter being enabled by said operating signal;

a second gate circuit for detecting a predetermined count of said second input control counter and for producing an output signal when said count is detected, the output signal from said second gate circuit being applied to said first gate circuit to inhibit application of said clock signal to said first intput control counter circuit;

a second bistable circuit responsive to the output signal from said second gate circuit for being set to produce a first gate control signal;

a third bistable circuit responsive to the output signal from said first gate circuit for being set to produce a second gate control signal;

circuit means for producing an actuation signal, comprising a short duration pulse produced at the start of said operating signal when said operating switch is actuated;

a third gate circuit responsive to said actuation signal and to the logical inverse of said first gate control signal for producing an output signal, said output signal being applied to reset said third bistable circuit, for thereby producing a fourth gate control signal;

a fourth gate circuit responsive to the first gate control signal, said second gate control signal, and said actuation signal for producing a pace memory reset signal;

a firth gate circuit responsive to the logical inverse of said second gate control signal from said third bistable circuit and to said actuation signal for producing a pace memory advance signal;

a pace memory counter, responsive to said pace memory reset signal for being reset to a count of zero and responsive to each occurrence of said pace memory advance signal for having a stored count incremented by one;

a comparator circuit for comparing the contents of said pace memory counter and said frequency divider counter and for producing a coincidence indication signal when coincidence between the contents thereof is detected;

a fourth bistable circuit responsive to an output signal from said frequency divider counter for being set to produce a first control signal, when a predetermined count of said frequency divider counter is attained, and responsive to said coincidence indication signal for being reset, thereby removing said pace gating control signal;

a fifth gate circuit coupled to receive said timebase signal and said pace gating control signal, being enabled to pass said timebase signal to an output terminal thereof by said pace getting control signal;

a pace timing divider circuit coupled to receive the output signal from said fifth gate circuit;

a delay circuit coupled to receive the output signal of said pace timing divider circuit and to produce an output signal delayed in time by a predetermined duration;

an eighth gate circuit coupled to receive the output signal from said delay circuit and said pace timing divider circuit and to receive, to thereby produce a first frequency signal;

a rhythm control circuit coupled to receive said first frequency signal and to produce a first frequency signal with rythm component;

a fourth bistable circuit responsive to alternate occurrences of the output signal from said first gate circuit for producing an output signal;

a fifth bistable circuit responsive to alternate occurrences of the output signal from said fourth bistable circuit for producing an output signal;

a first selector circuit coupled to receive said first frequency signal and said unit time signal, being responsive to the output signal from said fourth bistable circuit and to the logical inverse of said output signal for selectively passing said first frequency signal and said unit time signal to an output terminal thereof;

a combined elapsed time and step number counter cupled to receive the signal produced from said output terminal of said fifth gate circuit;

carry gate circuit means coupled to said combined elapsed time and step number counter, being responsive to the output signal from said fourth bistable circuit and to the logical inverse thereof for selectively causing said combined elapsed time and step number counter to count to a predetermined number of steps and to a predetermined elapsed time interval and to thereupon produce an elapsed time signal and a step number signal;

a repeater signal counter circuit, responsive to said actuatin signal for being reset to a count of zero;

a seventh gate circuit coupled to receive said first frequency signal and having an output terminal coupled to a clock input terminal of said repeater signal counter circuit;

comparator circuit means for comparing the count in said combined elapsed time and step number counter circuit with that in said repeater signal counter circuit and for producing a coincidence detection signal when coincidence therebetween is detected;

a fifth bistable circuit responsive to said coincidence detection signal for being set to produce an output control signal, said output control signal being applied to an input of said seventh gate circuit to enable said first frequency signal to be input to said repeater signal counter;

a second selector circuit, coupled to receive said first frequency signal and said first frequency signal having a rhythm component, and responsive to said output signal from said fifth bistable circuit and the logical inverse thereof for selectively passing said first frequency signal and said first frequency signal having a rythm component to an output terminal;

a sixth bistable circuit responsive to successive occurrences of said operating signal for alternately producing a control signal and the logical inverse of said control signal;

a ninth gate circuit, coupled to receive the output signal from said second selector circuit, and responsive to said control signal from said sixth bistable circuit for passing said output from said second selector circuit to an output terminal;

a first modulator gate circuit coupled to receive a first carrier signal from said frequency divider circuit and said repeater signal;

a second modulator gate circuit coupled to receive a modulated signal from said first modulator gate circuit, the output signal from said ninth gate circuit, and a second carrier signal from said frequency divider circuit, for thereby producing a pace signal and a modulated repeater signal;

a driver circuit coupled to receive said pace signal and modulated repeater signal, and to produce corresponding drive signals;

an electrodynamic loudspeaker driven by said drive signals to produce an audible pace timing signal and audible repeater signals indicating elapsed time intervals and numbers of steps executed.