Hermetic integrated circuit package for high density high power applications

• US 4,338,621 A
• Filed: 02/04/1980
• Issued: 07/06/1982
• Est. Priority Date: 02/04/1980
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Burroughs Incorporated (Terreno Realty Corp.)
• Inventors: Braun, Robert E.
• Primary Examiner(s): JAMES, ANDREW
• Application Number:
  US06/118,496
• Time in Patent Office: 883 Days
• Field of Search: 357/70, 357/74, 357/80, 357/81, 174/52 FP
• US Class Current: 257/697
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3672 Foil-like cooling fins or heat sinks being part of lead-frames H01L23/49568
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate

Abstract

The present disclosure describes an hermetically sealed integrated circuit package capable of accommodating high density circuit configurations with their attendant high power levels. In performing this function, the package permits the back-bonded integrated circuit chip or die to be mounted to a thermally conductive member of the package which is disposed in an open air stream. Moreover, the opposite side of the package positioned in proximity to the interconnection medium remains available to be fully populated by a large number of closely spaced input/output pins.

Claims

1. An hermetic package for an integrated circuit die which has a plurality of wires emanating from its periphery comprising:

a base member having an outer surface and a mounting surface, said base member having an internal recess for mounting said die in proximity to said outer surface, said base member further including a ledge encompassing said die, a plurality of electrically conductive tabs disposed on the surface of said ledge, said plurality of wires of said die being connected to respective ones of said tabs, a plurality of metallized lines each having an extremity connected respectively to one of said tabs and its remaining portion embedded in the material of said base member, said metallized lines lying in a plane substantially coplanar with the surface of said ledge, said mating surface of said base member lying in a plane parallel to but displaced from that of the surface of said ledge, the area of said last mentioned mating surface being substantially equal to that of said outer surface of said base member less the combined areas of the surface of said internal recess for mounting said die and the surface of said ledge, a plurality of metallized vias connecting the opposite extremities of said metallized lines to respective electrically conductive pads on said last mentioned mating surface,

a cover member having an outer surface and a mating surface, said cover member having a plurality of pads on said mating surface, said pads being homologously disposed with respect to said pads on said mating surface of said base member, a plurality of metallized lines on said mating surface of said cover member each having an extremity connected respectively to a pad on said last mentioned surface, a plurality of metallized vias connecting the opposite extremities of said metallized lines to bosses on said outer surface of said cover member, a plurality of input/output terminals affixed respectively to said bosses, said plurality of input/output terminals populating substantially the entire outer surface of said cover member, and

means for connecting homologously disposed pads on the mating surfaces of said base and cover members to each other and for sealing said last mentioned surfaces to each other.

2. An integrated circuit package as defined in claim 1 characterized in that said base member and said cover member are formed of thermally conductive material.

3. An integrated circuit package as defined in claim 2 further characterized in that said thermally conductive material is a ceramic.

4. An integrated circuit package as defined in claim 3 wherein said means for connecting homologously disposed pads on the mating surfaces of said base and cover members to each other includes solder deposited on said pads for establishing an electrical connection therebetween during a subsequent solder reflow operation.

5. An integrated circuit package as defined in claim 4 further characterized in that said means for sealing the respective mating surfaces of said base and cover members to each other include a seal ring disposed along the periphery of each of the last mentioned members and solder deposited thereon for subsequent reflow during a solder operation.

6. An integrated circuit package as defined in claim 5 wherein input/output terminals are pins.

7. An integrated circuit package as defined in claim 6 wherein each of said input/output pins includes a shoulder at one extremity thereof, said shoulder being brazed to a boss on the outer surface of said cover member, thereby sealing the via associated therewith.

8. An integrated circuit package as defined in claim 7 further including a plurality of cooling fins affixed to the outer surface of said base member to enhance the dissipation of heat therefrom.