Phase corrected clock signal recovery circuit

• US 4,339,823 A
• Filed: 08/15/1980
• Issued: 07/13/1982
• Est. Priority Date: 08/15/1980
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Jasper, Steven C., Predina, Joseph P.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US06/178,401
• Time in Patent Office: 697 Days
• Field of Search: 375/17, 375/20, 375/110, 375/120, 328/63, 328/133, 328/134, 329/50, 329/122, 329/124, 371/56, 331/1 R, 331/1 A
• US Class Current: 375/294
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Apparatus is provided for generating a recovered clock signal having pulses with a selected transitory edge timed to occur at the center of the eye intervals of a multilevel digital signal.

Claims

1. Apparatus for recovering the clock signal from a received multilevel digital signal comprising:

transition marker generating means, responsive to said received signal, for generating a transition marker signal each time said received signal crosses any of a plurality of predetermined threshold levels, said transition marker generating means thus producing a plurality of transition marker signal groups, each transition marker signal group being followed in time by an eye interval;

electronically tuned bandpass filter means, operatively coupled to the output of said transition marker generating means for attenuating undesired signal components of said transition marker groups exhibiting a frequency substantially above or substantially below the fundamental frequency of said transition marker groups, and for generating an approximately sinusoidal signal at the output of said filter means, the phase of said approximately sinusoidal signal varying in accordance with a phase error signal applied to a phase control terminal included in said filter means;

phase lock loop means, operatively coupled to the output of said filter means, for generating a recovered clock signal of pulses exhibiting a frequency substantially equal to and locked to the frequency of said approximately sinusoidal signal, and

phase error detecting means, including a first and second inputs operatively coupled to the output of said transition marker generating means and the output of said phase lock loop means, respectively, for generating at the output of said detecting means a phase error signal exhibiting indicia of the difference in phase between a selected transitory edge of said recovered clock signal and the center of said eye intervals, the output of said detecting means being operatively coupled to the phase control terminal of said filter means, such that the phase of said substantially sinusoidal signal is adjusted by said filter means until a selected transitory edge of the pulses of the recovered clock signal occurs at the centers of respective eye intervals.

2. The apparatus of claim 1 wherein said transition marker generating means comprises a narrow width transition marker generator for generating a transition marker pulse exhibiting relatively narrow pulse width each time said received signal crosses anyone of a plurality of threshold levels.