Device for testing digital circuits using built-in logic block observers (BILBO's)

• US 4,340,857 A
• Filed: 06/26/1981
• Issued: 07/20/1982
• Est. Priority Date: 04/11/1980
• Status: Expired due to Fees

• Current Assignee: Siemens Corp. (Siemens AG)
• Original Assignee: Siemens Corp. (Siemens AG)
• Inventors: Fasang, Patrick P.
• Primary Examiner(s): Tokar, Michael J.
• Application Number:
  US06/277,992
• Time in Patent Office: 389 Days
• Field of Search: 324/73 R, 324/73 AT, 371/25, 371/27
• US Class Current: 714/733
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318569 Error indication, logging circuits
• CPC Class Codes: G06F 11/27 Built-in tests

Abstract

A device for testing a digital electronic circuit, having a first BILBO for generating a pseudo-random test pattern, a second BILBO for analyzing a parallel-input signature, a decoder and at least one status indicator for indicating the status of a circuit under test.

Claims

1. A device for testing a digital electronic circuit, comprising in combination:

(a) first BILBO means for generating a pseudo-random test pattern, said first BILBO means being connected to inputs of said circuit under test and having a serially connected chain of storage elements and input modifying means connecting the output of at least one storage element to the input of another;

(b) second BILBO means for analyzing a parallel-input signature, said second BILBO means being connected to outputs of said circuit under test and having a serially connected chain of storage elements and input modifying means connecting the output of at least one storage element to the input of another;

(c) a decoder having;

(ca) inputs connected to outputs of said second BILBO means for receiving input signals having a predetermined combination of logic levels when said circuit under test is fault-free and having a combination of logic levels different from the predetermined combination when the circuit under test is faulty; and

(cb) an output for delivering a first output signal when said circuit under test is fault-free and for delivering a second output signal when said circuit under test is faulty;

(d) at least one status indicator connected to the output of said decoder for indicating the status of said circuit under test; and

(e) means for controlling said first and second BILBO means and said decoder in dependence on a master clock signal.

2. The testing device according to claim 1, wherein said first BILBO means comprises a plurality of inputs divided into a first group and into a second group, and wherein first input signals representing a logic 0 are supplied to said first group and wherein second input signals representing a logic 1 are supplied to said second group of inputs.

3. The testing device according to claim 1, wherein said second BILBO means comprises a plurality of inputs, a first combination of which are connected to outputs of said circuit under test and a second combination of which are supplied by input signals representing a first logic level.

4. The testing device according to claim 3, wherein a third combination of inputs of said second BILBO means is supplied by input signals representing a second logic level.

5. The testing device according to claim 1, wherein the outputs of said second BILBO means are non-complemented outputs, wherein the output signals of these non-complemented outputs have a predetermined combination of logic levels when said circuit under test is fault-free and a combination of logic levels different from said predetermined combination when said circuit under test is faulty, wherein each of a first group of the outputs of said second BILBO means is connected to an invertor, said first group having as output signals a first logic level when said circuit under test is fault-free, and wherein the outputs of said inverters and a second group of the outputs of said second BILBO means are connected to the inputs of said decoder, each of said second group having a second logic level when said circuit under test is fault-free.

6. The testing device according to claim 5, wherein the inputs of said decoder are the inputs of a summing member, the input signals of which having all the same logic level when said circuit under test is in a fault-free condition.

7. The testing device according to claim 6, wherein said summing member is a NAND gate.

8. The testing device according to claim 1, wherein said decoder has an output for delivering an output signal having a first logic level when said circuit under test is fault-free and having a second logic level when said circuit under test is faulty.

9. The testing device according to claim 1, wherein said master clock signal is derived from said circuit under test.

10. The testing device according to claim 1, wherein said master clock signal is derived from a master clock circuitry which is provided in addition to said circuit under test.

11. The testing device according to claim 1, wherein said control means includes a control circuit and a timing circuit which is controlled by timing pulses of said control circuit, said timing circuit delivering an output signal to said decoder after a predetermined number of clock pulses of said master clock signal, said output signal indicating the end of a test of said circuit under test.

12. The testing device according to claim 11, wherein the output of said timing circuit is applied to a blocking member in said decoder for releasing the output signal of said decoder to said status indicator.

13. The testing device according to claim 12, wherein said blocking member is an AND gate.

14. The testing device according to claim 11, wherein said timing circuit includes at least one counter.

15. The testing device according to claim 1, wherein the control circuit forms an enabling signal for driving said first and said second BILBO means, said enabling signal being comprised of a chain of pulses having a predetermined number, and wherein said control circuit also forms an end of test pulse at the last pulse of said chain of pulses, said end of test pulse being supplied to a blocking member for releasing the information which is just present in said decoder to said status indicator.

16. The testing device according to claim 15, wherein said chain of pulses has a predetermined number of 256 pulses.