Bipolar mark-space analogue-to-digital converter with balanced scale factors

• US 4,340,883 A
• Filed: 06/14/1978
• Issued: 07/20/1982
• Est. Priority Date: 06/20/1977
• Status: Expired due to Term

• Current Assignee: Solartron Group Limited (Emerson Electric Company)
• Original Assignee: The Solartron Electronic Group Limited (Thales SA)
• Inventors: Cook, John G.
• Primary Examiner(s): Sloyan, Thomas J.
• Application Number:
  US05/915,488
• Time in Patent Office: 1,497 Days
• Field of Search: 340/347 M, 340/347 NT, 340/347 AD, 340/347 CC, 324/99 D, 364/554, 364/460
• US Class Current: 341/127
• CPC Class Codes: H03M 1/1028 at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/52 Input signal integrated with linear return to datum

Abstract

In a bipolar mark-space analogue-to-digital converter, two opposed-polarity reference voltages are applied to an integrator during a first conversion interval to balance a square-wave forcing-function signal and an input signal whose magnitude is to be measured, and a counter receives clock pulses at up and down inputs during application of the positive and negative reference voltages respectively. Subsequently, zero input signal is applied during a second conversion interval, and the inputs to the counter are interchanged, so that up- and down-counted pulses correspond to the negative and positive reference voltages respectively. At the end of the second conversion interval, the counter contains a digital representation of the input signal, corrected for zero drift. The application of the reference voltages is controlled by two level detectors which compare the integrator output with fixed detector levels, the magnitudes of which are chosen so that at zero input each reference voltage is applied for substantially half the period of the square-wave forcing-function signal. The operation of the converter may be coordinated by a microprocessor which is arranged to aggregate the counts of clock pulses accumulated by the counter during each cycle of the forcing-function signal.

Claims

1. A bipolar mark-space analogue-to-digital converter having balanced scale factors for positive and negative applied voltages comprising:

integrating means for receiving an analog input signal to be converted;

means for superimposing a periodic signal on the output signal produced by the integrating means;

first and second reference signal sources of opposite polarity;

first and second level detectors connected to compare the output signal from the integrating means with first and second detector levels respectively, wherein, to balance scale factors substantially independently of drift or imbalance in said reference signal sources, for zero input signal, the periodic signal causes the magnitude of the output signal from the integrating means to exceed the first level by crossing it in a direction away from the second level for at least a substantial fraction of one half of each cycle of the periodic signal, and to fall below the second level by crossing it in a direction away from the first level for at least a substantial fraction of the other half of each cycle of the periodic signal, and wherein analogue input signals of one polarity cause the magnitude of the output signal to exceed the first level for more than said fraction of said one half of each cycle, while analogue input signals of the other polarity cause the magnitude of the output signal to fall below the second level for more than said fraction of said other half of each cycle, the first and second level detectors being arranged to produce first and second control signals respectively when the magnitude of the output signal from the integrating means exceeds the first level and falls below the second level respectively;

switch means responsive to the first control signal to apply one of said reference signal sources, opposite in polarity to said one polarity of the analogue input signal to the integrating means, said switch means being also responsive to the second control signal to apply the other of said reference signal sources to the integrating means;

means for defining a conversion interval equal in duration to the duration of an integral number of cycles of said periodic signal;

further switch means for applying said analogue input signal to the integrating means for the duration of one conversion interval and for applying zero input signal to the integrating means for the duration of another conversion interval;

a source of clock pulses; and

counter means responsive to the first and second control signals for counting the clock pulses during the application of either of the reference signal sources to the integrating means, whereby the count in the counter means at the end of the one conversion interval, combined with the count at the end of the other conversion interval, is a digital representation of the magnitude of the integral of the analogue input signal over the one conversion interval, corrected for zero drift.

2. A converter according to claim 1, wherein the level detectors comprise respective transistors.

3. A converter according to claim 1 wherein the counter means comprises a reversible counter, and means for causing the counter initially to count in one direction during the application of the first reference signal source and in the other direction during the application of the second reference signal source.

4. A converter according to claim 2, wherein at least one of the detector levels is defined by the threshold voltage required to initiate conduction through the transistors.