Dual mapping memory expansion unit

• US 4,340,932 A
• Filed: 05/17/1978
• Issued: 07/20/1982
• Est. Priority Date: 05/17/1978
• Status: Expired due to Term

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Maly, Dennis L., Weemhoff, James H., Bakula, Richard E.
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): Eng, David Y.
• Application Number:
  US05/906,830
• Time in Patent Office: 1,525 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/2
• CPC Class Codes: G06F 12/0623 for memory modules

Abstract

In a unified bus data processing system, a memory expansion unit is connected to the bus to convert bus addresses into addresses in a physical memory which may be many times larger than the maximum size that the bus would have been capable of addressing previously. Thus, the memory expansion unit provides directly addressable memory locations which serve to expand the range of physical addresses allocated to the bus by selectively connecting a plurality of expansion memory units to said bus. The memory expansion unit is programmed to convert groups of bus addresses into the same size group of addresses anywhere in physical memory. Until the memory expansion unit is programmed, physical memory is directly addressable by the central processing unit by applying the appropriate bus address and the normal control signals thereto. The memory expansion unit can also perform a dual mapping function by allocating the expansion memory space differently for the central processor unit than for the other devices connected to the bus. Such control and memory expansion is made available while also retaining the possibility of partial physical memory space on the bus for a portion of the bus address space.

Claims

1. In a data processing system including an I/O bus having a plurality of conductors for carrying both data and address signals;

a plurality of I/O devices including devices forming physically addressed storage locations connected to said bus in parallel, each of said I/O devices being assigned to a respective address slot consisting of a predetermined block of the available addresses on said bus;

a central processor unit for processing a program stored in at least one of said storage locations, the addresses of said storage locations being divided into first, second, and third portions; and

address conversion means connected in series between said central processor unit and said bus for transmitting onto the bus, in response to a virtual address from said central processor unit, a physical address for selecting a storage location;

the improvement comprising

a plurality of expansion memory units providing a total number of memory locations exceeding the number of physical addresses making up an address slot on said bus;

a memory expansion unit connected to said bus in parallel with said I/O devices and having an address slot assigned thereto for converting the block of physical addresses corresponding to said address slot on said bus into an expanded range of physical addresses for selecting said memory locations in said expansion memory units; and

means for connecting the respective expansion memory units to said memory expansion unit;

said memory expansion unit including a mapping register in the form of a random access memory storing the base physical address for a block of consecutively addressed memory locations, said mapping register being responsive to the first portion of said physical address received from said bus for reading out a selected base physical address; and

adder means for combining the output of said mapping register and the second portion of the physical address received from said bus to produce an intermediate address;

at least a portion of said intermediate address juxtaposed with the third portion of said physical address received from said bus being forwarded to said expansion memory units as an expanded physical address.

2. A data processing system as defined in claim 1 wherein said memory expansion unit further includes operation controller means responsive to said central processor unit for determining the allocation of address bits received on said bus to said first, second and third portions of said physical address;

and address multiplexer means responsive to said operation controller means for selectively applying to said mapping register those address bits on said bus which make up said first portion of said physical address.

3. A data processing system as defined in claim 2 wherein said address multiplexer means includes means connected to said adder means for supplying from said bus address bits of the second portion of said physical address not allocated to the first portion thereof in accordance with the determination of said operation controller means.

4. A data processing system as defined in claim 3 wherein said memory expansion unit further includes bypass gate means responsive to said operation controller means for applying the first portion of said physical address directly from said bus to the input of said adder means bypassing said mapping register in response to control from said central processor unit.

5. A data processing system as defined in claim 1 wherein said means for connecting the respective expansion memory unit comprises a plurality of expansion memory buses and wherein said memory expansion unit further includes memory selector means responsive to at least one selected bit of said intermediate address for enabling a designated one of said expansion memory buses.

6. A data processing system as defined in claim 5 wherein said memory expansion unit further includes means responsive to a selected bit of the base physical address derived from said mapping register designating a selected block of physical addresses for selectively inhibiting said memory selector means.

7. A data processing system as defined in claim 1 wherein said memory expansion unit includes first and second mapping registers in the form of random access memories each storing base physical addresses for the block of physical addresses allocated to the storage location formed by said memory expansion unit, said first and second mapping registers each being responsive to different length first portions of said physical addresses received from said bus for reading out a selected base physical address;

expanded address generating means connected to said bus and said mapping registers for combining said selected base physical address with the second and third portions of the physical address received from said bus into an expanded physical address and for applying said expanded physical address to said expansion memory units.

8. A data processing system as defined in claim 7 wherein said memory expansion unit further includes memory control means responsive to control signals applied to said bus by said central processor unit and said I/O devices connected to said bus for enabling said first mapping register only when said central processor unit is in control of said bus and for enabling said second mapping register only when an I/O device connected to said bus is in control of said bus.

9. A data processing system as defined in claim 8 wherein said means for connecting the respective expansion memory unit comprises a plurality of expansion memory buses and wherein said memory expansion unit further includes memory selector means responsive to at least one selected bit of said address for enabling a designated one of said expansion memory buses.

10. A data processing system as defined in claim 9 wherein said memory expansion unit further includes operation controller means responsive to said central processor unit for determining the allocation of address bits required on said bus to said first, second, and third portions of said physical address;

and address multiplexer means responsive to said operation controller means for selectively applying to said mapping register those address bits on said bus which make up said first portion of said physical address.

11. A data processing system as defined in claim 10 wherein said address multiplexer means includes means connected to said adder means for supplying from said bus address bits of the second portion of said physical address not allocated to the first portion thereof in accordance with the determination of said operation controller means.

12. A data processing system as defined in claim 11 wherein said memory expansion unit further includes means for applying the address bits corresponding to the third portion of said physical address from said bus directly to said expansion memory units.

13. A data processing system as defined in claim 12 wherein said memory expansion unit further includes bypass gate means responsive to said operation controller means for applying the first portion of said physical address directly from said bus to the input of said adder means bypassing said mapping register in response to control from said central processor unit.

14. In a data processing system including an I/O bus having a plurality of conductors for carrying both data and address signals;

a plurality of I/O devices including devices forming physically addressed storage locations connected in parallel to said bus, each of said I/O devices being assigned to a respective address slot consisting of a predetermined block of the available addresses on said bus; and

a central processor unit for processing a program stored in at least one of said storage locations, the addresses of said storage locations being divided into first, second, and third portions;

the improvement comprising

a plurality of expansion memory units providing a total number of memory locations exceeding the number of physical addresses making up an address slot;

a memory expansion unit connected in parallel with said I/O devices and having an address slot assigned thereto for converting the block of physical addresses corresponding to said address slot on said bus into an expanded range of physical addresses for selecting said memory locations in said expansion memory units, including means for generating a different set of expanded physical addresses in response to addresses received on said bus from said central processor unit than the set generated in response to addreses received on said bus from one of said I/O devices connected to said bus; and

means for connecting the respective expansion memory units to said memory expansion unit.

15. A data processing system as defined in claim 14 wherein said memory expansion unit includes a mapping register in the form of a random access memory storing base physical addresses for a block of consecutively addressed memory locations, said mapping register being responsive to the first portion of said physical address received from said bus for reading out a selected base physical address;

adder means for combining the output of said mapping register and the second portion of the physical address received from said bus to produce an expanded physical address to be forwarded to said expansion memory units.

16. A data processing system as defined in claim 15 wherein said memory expansion unit further includes bypass gate means for applying the first portion of said physical address directly from said bus to the input of said adder means bypassing said mapping register in response to control from said central processor unit.

17. A data processing system as defined in claim 15 wherein said means for connecting the respective expansion memory unit comprises a plurality of expansion memory buses and wherein said memory expansion unit further includes memory selector means responsive to at least one selected bit of said expanded physical address for enabling a designated one of said expansion memory buses.

18. A data processing system as defined in claim 17 wherein said memory expansion unit further includes operation controller means responsive to said central processor unit for determining the allocation of address bits received on said bus to said first, second, and third portions of said physical address;

and address multiplexer means responsive to said operation controller means for selectively applying to said mapping register those address bits on said bus which make up said first portion of said physical address.

19. A data processing system as defined in claim 18 wherein said address multiplexer means includes means connected to said adder means for supplying from said bus address bits of the second portion of said physical address not allocated to the first portion thereof in accordance with the determination of said operation controller means.

20. A data processing system as defined in claim 19 wherein said memory expansion unit further includes means for applying the address bits corresponding to the third portion of said physical address from said bus directly to said expansion memory units.

21. A data processing system as defined in claim 15 wherein said memory expansion unit includes first and second mapping registers in the form of random access memories each storing base physical addresses for the block of physical addresses allocated to the storage location formed by said memory expansion unit, said first and second mapping registers each being responsive to different length first portions of said physical addresses received from said bus for reading out a selected base physical address;

expanded address generating means connected to said bus and said mapping registers for comining said selected base physical address with the second and third portions of the physical address received from said bus into an expanded physical address.

22. A data processing system as defined in claim 21 wherein said control means includes means responsive to control signals applied to said bus by said central processor unit and said devices connected thereto for enabling said first mapping register only when said central processor unit is in control of said bus and for enabling said second mapping register only when a device connected to said bus is in control of said bus.