Partial scrolling video generator

• US 4,342,991 A
• Filed: 04/10/1980
• Issued: 08/03/1982
• Est. Priority Date: 03/10/1980
• Status: Expired due to Term

• Current Assignee: Display Technologies, Inc. (Rhode Island)
• Original Assignee: Multisonics, Inc.
• Inventors: Williamson, Richard A., Pope, Richard N.
• Primary Examiner(s): Curtis, Marshall M.
• Application Number:
  US06/128,347
• Time in Patent Office: 845 Days
• Field of Search: 340/726, 340/724, 340/723, 340/744, 340/748, 340/792
• US Class Current: 345/28
• CPC Class Codes: G09G 5/343 for systems having a character code-mapped display memory

Abstract

A raster scan cathode ray tube (CRT) display system which is capable of indirectly addressing data to be displayed in an manner presenting the data on any selected row or group of rows, in any order. A scrolling system according to the invention includes a cathode ray tube controller (CRTC) coupled to an indirect address counter which is coupled together with a presettable counter through a multiplexer (MUX) to the address port of a CRT display refresh memory (RAM), a segment of the data output port of the refresh memory being coupled to the preset port of the presettable counter. The invention operates by generating a refresh address indirectly through the presettable counter which addresses pointers in the refresh memory, each pointer containing the absolute address of the beginning of a specific line of data in the refresh memory which is to be displayed. During the blanking interval of the display, data is addressed by the indirect address counter. During other intervals, the address presented to the refresh memory is generated by the refresh address counter (the presettable binary counter). The address which is provided at the refresh address counter dictates the line of characters which are therafter displayed.

Claims

1. A method for use in scrolling display rows in a raster scan type cathode ray tube display system wherein the display system includes a video display, refresh logic, a refresh memory, a first counter and a second counter, said refresh memory having storage locations arranged in a first matrix and a second matrix, said first matrix comprising storage for indirect address pointers of preselected base address locations for rows of said second matrix, said second matrix comprising fixed address storage for data to be presented for output to said video display, said method comprising the steps of:

(a) writing a base address pointer for each row into said first matrix;

(b) reading, according to an address value in said first counter, a base address pointer from a location in said first matrix which points to the base address of a row in said second matrix so as to supply the base address to the address input of said refresh memory;

thereupon

(c) reading for output to said video display, according to a value in said second counter containing the current column address, data in said second matrix at the current column and row address;

(d) incrementing said second counter containing the current column and row address to advance the column address;

(e) repeating steps (c) and (d) until the end of the row is serviced;

(f) incrementing said first counter to access a next sequential address in said first matrix;

(g) repeating steps (b) through (f) to present a plurality of rows of data in said second matrix to said video display.

2. The method as claimed in claim 1 wherein said writing step further includes modifying selected ones of said base addresses in said first matrix from time to time in order to alter the sequence of presentation of selected ones of said rows.

3. The method as claimed in claim 2 further including the step of limiting the number of base addresses which are altered.

4. The method as claimed in claim 2 further including the step of starting at other than the first address value location in said first matrix in order to limit the number rows which are refreshed.

5. A method for use in scrolling rows in a raster scan type cathode ray tube display system wherein the system includes a video display, refresh logic and a refresh memory operative in response to write signals to store data information for subsequent display according to address information and operative in response to read signals at an address input to present data information at a data output, said refresh memory having storage locations arranged in a first matrix and a second matrix, said first matrix comprising storage for indirect address pointers of base addresses of rows of said second matrix, said second matrix comprising storage for data to be presented to said video display, said method comprising the steps of:

(a) writing display data into said refresh memory in said second matrix;

(b) writing base address information into said refresh memory in said first matrix, said base address information being arranged in a queue in said first matrix;

(c) causing said refresh memory to read a base address of a row from a current location of said first matrix as an indirect address and supplying said base address as a current location to the address input of said refresh memory;

(d) causing said refresh logic to read into said video display the data at the current location of the specified row in said second matrix in order to provide a video output signal;

(e) incrementing a column counter in response to a character clock in order to increment column location from said base address location in said second matrix;

(f) repeating steps (c) and (d) until said column counter is preset;

(g) incrementing an indirect address counter synchronously with a preset signal to said column counter in order to advance the current location of said first matrix;

(h) repeating steps (c) through (g) in order to present all rows of said second matrix for refreshing said display.

6. The method according to claim 5 wherein the base address writing step further includes the step of modifying selected ones of said base addresses in said first matrix from time to time in order to alter the sequence of display of said rows.

7. An apparatus for use in a raster scan type cathode ray tube display system in connection with a processor having an address bus and a data bus, and a video display device, said apparatus comprising:

refresh logic and a refresh memory, said refresh memory comprising address input terminals and data output terminals and digital data storage locations arranged in a first matrix and a second matrix, said first matrix being limited to storage for indirect address pointers of preselected base address locations of rows of said second matrix, said second matrix comprising fixed address storage for data to be presented to said video display device, said refresh logic comprising a refresh address counter coupled between said data output terminals of said refresh memory and said address input terminals of said refresh memory for addressing column locations of said refresh memory, said refresh logic further comprising an indirect address counter coupled to said address input terminals of said refresh memory for addressing said first matrix and thereby row pointers of said second matrix.

8. The apparatus as claimed in claim 7 further including a multiplexer disposed in an address bus between the input address port of said refresh memory at output port terminal, said indirect address counter at a first input port and a refresh address counter at a second input port, said multiplexer being subject to switch-over under control of a video blanking signal.